AU2001291311A1 - Programmable and multiplierless viterbi accelerator - Google Patents
Programmable and multiplierless viterbi acceleratorInfo
- Publication number
- AU2001291311A1 AU2001291311A1 AU2001291311A AU9131101A AU2001291311A1 AU 2001291311 A1 AU2001291311 A1 AU 2001291311A1 AU 2001291311 A AU2001291311 A AU 2001291311A AU 9131101 A AU9131101 A AU 9131101A AU 2001291311 A1 AU2001291311 A1 AU 2001291311A1
- Authority
- AU
- Australia
- Prior art keywords
- multiplierless
- programmable
- viterbi accelerator
- viterbi
- accelerator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
- H03M13/256—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with trellis coding, e.g. with convolutional codes and TCM
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
- H03M13/4161—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management
- H03M13/4169—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management using traceback
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/63—Joint error correction and other techniques
- H03M13/635—Error control coding in combination with rate matching
- H03M13/6362—Error control coding in combination with rate matching by puncturing
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6502—Reduction of hardware complexity or efficient processing
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6569—Implementation on processors, e.g. DSPs, or software implementations
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US23125500P | 2000-09-08 | 2000-09-08 | |
US60231255 | 2000-09-08 | ||
US60/231,255 | 2000-09-08 | ||
PCT/US2001/042141 WO2002021699A2 (en) | 2000-09-08 | 2001-09-10 | Programmable and multiplierless viterbi accelerator |
Publications (1)
Publication Number | Publication Date |
---|---|
AU2001291311A1 true AU2001291311A1 (en) | 2002-03-22 |
Family
ID=22868421
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU2001291311A Abandoned AU2001291311A1 (en) | 2000-09-08 | 2001-09-10 | Programmable and multiplierless viterbi accelerator |
Country Status (3)
Country | Link |
---|---|
US (1) | US6883021B2 (en) |
AU (1) | AU2001291311A1 (en) |
WO (1) | WO2002021699A2 (en) |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100375823B1 (en) * | 2000-12-27 | 2003-03-15 | 한국전자통신연구원 | Structures and Methods to Depuncture Punctured Codes for Radix-4 Branch Metric Calculation in High-Speed Viterbi Decoder |
US7046747B2 (en) * | 2002-04-16 | 2006-05-16 | Intel Corporation | Viterbi decoder and decoding method using rescaled branch metrics in add-compare-select operations |
US6838723B2 (en) * | 2002-08-29 | 2005-01-04 | Micron Technology, Inc. | Merged MOS-bipolar capacitor memory cell |
US7623585B2 (en) | 2003-02-28 | 2009-11-24 | Maher Amer | Systems and modules for use with trellis-based decoding |
DE10310812B4 (en) | 2003-03-12 | 2007-11-22 | Infineon Technologies Ag | Decoding device, trellis processor and method |
US7117427B2 (en) * | 2003-07-09 | 2006-10-03 | Texas Instruments Incorporated | Reduced complexity decoding for trellis coded modulation |
US20050071734A1 (en) * | 2003-09-26 | 2005-03-31 | Broadcom Corporation | Methods and systems for Viterbi decoding |
US7287212B2 (en) * | 2003-09-26 | 2007-10-23 | Broadcom Corporation | Methods and systems for Viterbi decoding |
US7522679B2 (en) | 2003-10-01 | 2009-04-21 | Paradyne Corporation | System and method for adapting to a change in constellation density while receiving a signal |
US20050076224A1 (en) * | 2003-10-07 | 2005-04-07 | Royer George R. | Coding system |
US7496159B2 (en) * | 2003-12-01 | 2009-02-24 | Mediatek Inc. | Survivor memory management in a Viterbi decoder |
US7870176B2 (en) * | 2004-07-08 | 2011-01-11 | Asocs Ltd. | Method of and apparatus for implementing fast orthogonal transforms of variable size |
US7908542B2 (en) | 2004-08-25 | 2011-03-15 | Asocs Ltd | Method of and apparatus for implementing a reconfigurable trellis-type decoding |
US7603613B2 (en) * | 2005-02-17 | 2009-10-13 | Samsung Electronics Co., Ltd. | Viterbi decoder architecture for use in software-defined radio systems |
US8140947B2 (en) | 2005-09-30 | 2012-03-20 | Agere Systems Inc. | Method and apparatus for storing survivor paths in a Viterbi detector using systematic pointer exchange |
US8069401B2 (en) * | 2005-12-21 | 2011-11-29 | Samsung Electronics Co., Ltd. | Equalization techniques using viterbi algorithms in software-defined radio systems |
US8111767B2 (en) * | 2007-05-31 | 2012-02-07 | Renesas Electronics Corporation | Adaptive sliding block Viterbi decoder |
DE102007026406B4 (en) * | 2007-06-06 | 2009-04-30 | Continental Automotive Gmbh | Apparatus and method for encoding a data word and storing the coded data word |
US8290060B2 (en) * | 2007-08-21 | 2012-10-16 | Limberg Allen Leroy | Staggercasting of DTV signals that employ concatenated convolutional coding |
CN102404011B (en) * | 2010-09-15 | 2015-05-20 | 中兴通讯股份有限公司 | Method and device for achieving Viterbi decoding |
GB2520708A (en) * | 2013-11-28 | 2015-06-03 | Ibm | Multi-stage codeword detector |
TWI565246B (en) * | 2015-01-12 | 2017-01-01 | 晨星半導體股份有限公司 | Decoding method for a convolutional code |
CN107506176B (en) * | 2016-06-14 | 2019-07-12 | 华为技术有限公司 | A kind of method and apparatus of determining decoding task |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5220570A (en) * | 1990-11-30 | 1993-06-15 | The Board Of Trustees Of The Leland Stanford Junior University | Programmable viterbi signal processor |
US5454014A (en) * | 1993-11-16 | 1995-09-26 | At&T Corp. | Digital signal processor |
US5432804A (en) * | 1993-11-16 | 1995-07-11 | At&T Corp. | Digital processor and viterbi decoder having shared memory |
TW243568B (en) * | 1993-11-16 | 1995-03-21 | At & T Corp | Digital signal processor with an embedded viterbi co-processor |
US5859861A (en) * | 1995-06-21 | 1999-01-12 | Hyundai Electronics Ind. Co., Ltd. | High speed viterbi decoder |
US6690750B1 (en) * | 1999-12-23 | 2004-02-10 | Texas Instruments Incorporated | Flexible Viterbi decoder for wireless applications |
US6829305B2 (en) * | 1999-12-08 | 2004-12-07 | Lg Electronics Inc. | Concatenated convolutional encoder and decoder of mobile communication system |
US6996158B2 (en) * | 2001-02-22 | 2006-02-07 | Freescale Semiconductors, Inc. | Signal detection using a CDMA receiver |
-
2001
- 2001-09-10 WO PCT/US2001/042141 patent/WO2002021699A2/en active Application Filing
- 2001-09-10 US US09/951,348 patent/US6883021B2/en not_active Expired - Fee Related
- 2001-09-10 AU AU2001291311A patent/AU2001291311A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US6883021B2 (en) | 2005-04-19 |
WO2002021699A2 (en) | 2002-03-14 |
US20020095639A1 (en) | 2002-07-18 |
WO2002021699A3 (en) | 2002-07-18 |
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