SG150449A1 - Method for creating a memory defect map and optimizing performance using the memory defect map - Google Patents
Method for creating a memory defect map and optimizing performance using the memory defect mapInfo
- Publication number
- SG150449A1 SG150449A1 SG200805821-6A SG2008058216A SG150449A1 SG 150449 A1 SG150449 A1 SG 150449A1 SG 2008058216 A SG2008058216 A SG 2008058216A SG 150449 A1 SG150449 A1 SG 150449A1
- Authority
- SG
- Singapore
- Prior art keywords
- defect map
- memory
- memory defect
- creating
- optimizing performance
- Prior art date
Links
- 230000007547 defect Effects 0.000 title abstract 10
- 238000000034 method Methods 0.000 title abstract 3
- 101000578834 Synechocystis sp. (strain PCC 6803 / Kazusa) Methionine aminopeptidase A Proteins 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/20—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits using counters or linear-feedback shift registers [LFSR]
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/1208—Error catch memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/838,585 US7949913B2 (en) | 2007-08-14 | 2007-08-14 | Method for creating a memory defect map and optimizing performance using the memory defect map |
Publications (1)
Publication Number | Publication Date |
---|---|
SG150449A1 true SG150449A1 (en) | 2009-03-30 |
Family
ID=40196686
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG200805821-6A SG150449A1 (en) | 2007-08-14 | 2008-08-04 | Method for creating a memory defect map and optimizing performance using the memory defect map |
Country Status (5)
Country | Link |
---|---|
US (1) | US7949913B2 (zh) |
EP (1) | EP2026356B1 (zh) |
CN (1) | CN101369247B (zh) |
SG (1) | SG150449A1 (zh) |
TW (1) | TWI370455B (zh) |
Cited By (1)
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---|---|---|---|---|
US8904228B2 (en) | 2011-12-07 | 2014-12-02 | Dell Products L.P. | Methods and systems for repairing memory |
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US8140890B2 (en) * | 2009-12-29 | 2012-03-20 | International Business Machines Corporation | Relocating bad block relocation (BBR) directory upon encountering physical media defect on a disk |
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US8937845B2 (en) * | 2012-10-31 | 2015-01-20 | Freescale Semiconductor, Inc. | Memory device redundancy management system |
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CN106548809A (zh) | 2015-09-22 | 2017-03-29 | 飞思卡尔半导体公司 | 处理缺陷非易失性存储器 |
US9928924B2 (en) * | 2015-12-15 | 2018-03-27 | Qualcomm Incorporated | Systems, methods, and computer programs for resolving dram defects |
KR102420897B1 (ko) * | 2016-03-17 | 2022-07-18 | 에스케이하이닉스 주식회사 | 메모리 모듈, 이를 포함하는 메모리 시스템 및 그의 동작 방법 |
CN108735268B (zh) | 2017-04-19 | 2024-01-30 | 恩智浦美国有限公司 | 非易失性存储器修复电路 |
KR20190032793A (ko) * | 2017-09-20 | 2019-03-28 | 에스케이하이닉스 주식회사 | 메모리 모듈 |
US10978028B2 (en) | 2018-09-17 | 2021-04-13 | Apple Inc. | Correction for defective memory of a memory-in-pixel display |
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-
2007
- 2007-08-14 US US11/838,585 patent/US7949913B2/en active Active
-
2008
- 2008-08-04 SG SG200805821-6A patent/SG150449A1/en unknown
- 2008-08-08 TW TW097130224A patent/TWI370455B/zh active
- 2008-08-13 CN CN200810210500.2A patent/CN101369247B/zh active Active
- 2008-08-14 EP EP08014502.2A patent/EP2026356B1/en active Active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8904228B2 (en) | 2011-12-07 | 2014-12-02 | Dell Products L.P. | Methods and systems for repairing memory |
Also Published As
Publication number | Publication date |
---|---|
US7949913B2 (en) | 2011-05-24 |
CN101369247A (zh) | 2009-02-18 |
CN101369247B (zh) | 2013-06-05 |
TW200917262A (en) | 2009-04-16 |
EP2026356B1 (en) | 2016-07-20 |
US20090049351A1 (en) | 2009-02-19 |
EP2026356A3 (en) | 2009-12-02 |
TWI370455B (en) | 2012-08-11 |
EP2026356A2 (en) | 2009-02-18 |
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