DE69421379T2 - Wiederverwendbarer Mehrwegsatz assoziativer Cache-Speicher - Google Patents

Wiederverwendbarer Mehrwegsatz assoziativer Cache-Speicher

Info

Publication number
DE69421379T2
DE69421379T2 DE69421379T DE69421379T DE69421379T2 DE 69421379 T2 DE69421379 T2 DE 69421379T2 DE 69421379 T DE69421379 T DE 69421379T DE 69421379 T DE69421379 T DE 69421379T DE 69421379 T2 DE69421379 T2 DE 69421379T2
Authority
DE
Germany
Prior art keywords
reusable
associative caches
associative
caches
reusable set
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69421379T
Other languages
English (en)
Other versions
DE69421379D1 (de
Inventor
David Charles Mcclure
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
STMicroelectronics lnc USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics lnc USA filed Critical STMicroelectronics lnc USA
Publication of DE69421379D1 publication Critical patent/DE69421379D1/de
Application granted granted Critical
Publication of DE69421379T2 publication Critical patent/DE69421379T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
DE69421379T 1994-03-31 1994-12-06 Wiederverwendbarer Mehrwegsatz assoziativer Cache-Speicher Expired - Lifetime DE69421379T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US22107294A 1994-03-31 1994-03-31

Publications (2)

Publication Number Publication Date
DE69421379D1 DE69421379D1 (de) 1999-12-02
DE69421379T2 true DE69421379T2 (de) 2000-05-11

Family

ID=22826220

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69421379T Expired - Lifetime DE69421379T2 (de) 1994-03-31 1994-12-06 Wiederverwendbarer Mehrwegsatz assoziativer Cache-Speicher

Country Status (4)

Country Link
US (1) US5666482A (de)
EP (1) EP0675436B1 (de)
JP (1) JPH0822417A (de)
DE (1) DE69421379T2 (de)

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JPH09319569A (ja) * 1996-05-31 1997-12-12 Mitsubishi Electric Corp マイクロコンピュータ
US6412051B1 (en) * 1996-11-27 2002-06-25 International Business Machines Corp. System and method for controlling a memory array in an information handling system
US6038680A (en) * 1996-12-11 2000-03-14 Compaq Computer Corporation Failover memory for a computer system
US6006311A (en) * 1997-04-14 1999-12-21 Internatinal Business Machines Corporation Dynamic updating of repair mask used for cache defect avoidance
US6223248B1 (en) * 1997-04-29 2001-04-24 Texas Instruments Incorporated Circuits systems and methods for re-mapping memory row redundancy during two cycle cache access
US6289438B1 (en) 1998-07-29 2001-09-11 Kabushiki Kaisha Toshiba Microprocessor cache redundancy scheme using store buffer
US6510493B1 (en) 1999-07-15 2003-01-21 International Business Machines Corporation Method and apparatus for managing cache line replacement within a computer system
US6473834B1 (en) 1999-12-22 2002-10-29 Unisys Method and apparatus for prevent stalling of cache reads during return of multiple data words
US6415357B1 (en) 1999-12-23 2002-07-02 Unisys Corporation Caching method and apparatus
JP3457611B2 (ja) * 2000-02-16 2003-10-20 日本電気株式会社 半導体記憶装置
US6671822B1 (en) * 2000-08-31 2003-12-30 Hewlett-Packard Development Company, L.P. Method and system for absorbing defects in high performance microprocessor with a large n-way set associative cache
US6918071B2 (en) * 2001-04-20 2005-07-12 Sun Microsystems, Inc. Yield improvement through probe-based cache size reduction
US6385071B1 (en) 2001-05-21 2002-05-07 International Business Machines Corporation Redundant scheme for CAMRAM memory array
US20030084389A1 (en) * 2001-10-25 2003-05-01 Sailesh Kottapalli Method and apparatus for flexible memory for defect tolerance
JP3953903B2 (ja) * 2002-06-28 2007-08-08 富士通株式会社 キャッシュメモリ装置、及び、参照履歴のビット誤り検出方法
US7168010B2 (en) 2002-08-12 2007-01-23 Intel Corporation Various methods and apparatuses to track failing memory locations to enable implementations for invalidating repeatedly failing memory locations
FR2846114A1 (fr) * 2002-10-16 2004-04-23 Thomson Licensing Sa Dispositif de memorisation d'une liste d'elements et procede de memorisation d'un element dans un tel dispositif
US7467377B2 (en) * 2002-10-22 2008-12-16 Intel Corporation Methods and apparatus for compiler managed first cache bypassing
US6922754B2 (en) * 2002-12-09 2005-07-26 Infabric Technologies, Inc. Data-aware data flow manager
US7131039B2 (en) * 2002-12-11 2006-10-31 Hewlett-Packard Development Company, L.P. Repair techniques for memory with multiple redundancy
WO2005024843A1 (en) * 2003-09-04 2005-03-17 Koninklijke Philips Electronics N.V. Integrated circuit and a method of cache remapping
US7401189B2 (en) * 2005-02-09 2008-07-15 International Business Machines Corporation Pipelining D states for MRU steerage during MRU/LRU member allocation
US7363433B2 (en) * 2005-02-09 2008-04-22 International Business Machines Corporation Cache member protection with partial make MRU allocation
US7343455B2 (en) * 2005-02-09 2008-03-11 International Business Machines Corporation Cache mechanism and method for avoiding cast out on bad victim select and recycling victim select operation
JP2008269142A (ja) * 2007-04-18 2008-11-06 Hitachi Ltd ディスクアレイ装置
US7856576B2 (en) * 2007-04-25 2010-12-21 Hewlett-Packard Development Company, L.P. Method and system for managing memory transactions for memory repair
US7949913B2 (en) * 2007-08-14 2011-05-24 Dell Products L.P. Method for creating a memory defect map and optimizing performance using the memory defect map
US9373362B2 (en) * 2007-08-14 2016-06-21 Dell Products L.P. System and method for implementing a memory defect map
US7945815B2 (en) * 2007-08-14 2011-05-17 Dell Products L.P. System and method for managing memory errors in an information handling system
US7987320B2 (en) * 2007-12-06 2011-07-26 International Business Machines Corporation Cache mechanism and method for avoiding cast out on bad victim select and recycling victim select operation
US7809980B2 (en) * 2007-12-06 2010-10-05 Jehoda Refaeli Error detector in a cache memory using configurable way redundancy
US8392658B2 (en) * 2009-07-10 2013-03-05 Apple Inc. Cache implementing multiple replacement policies
US8839025B2 (en) * 2011-09-30 2014-09-16 Oracle International Corporation Systems and methods for retiring and unretiring cache lines
US8724408B2 (en) 2011-11-29 2014-05-13 Kingtiger Technology (Canada) Inc. Systems and methods for testing and assembling memory modules
US9117552B2 (en) 2012-08-28 2015-08-25 Kingtiger Technology(Canada), Inc. Systems and methods for testing memory
US10185619B2 (en) * 2016-03-31 2019-01-22 Intel Corporation Handling of error prone cache line slots of memory side cache of multi-level system memory
KR101805028B1 (ko) * 2016-06-28 2017-12-06 고려대학교 산학협력단 물리 영역과 가상 영역을 근거로 결함 리페어를 적용하는 메모리 장치 및 그의 제어 방법

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US4168541A (en) * 1978-09-25 1979-09-18 Sperry Rand Corporation Paired least recently used block replacement system
US4506364A (en) * 1982-09-30 1985-03-19 International Business Machines Corporation Memory address permutation apparatus
US4633429A (en) * 1982-12-27 1986-12-30 Motorola, Inc. Partial memory selection using a programmable decoder
US4538247A (en) * 1983-01-14 1985-08-27 Fairchild Research Center Redundant rows in integrated circuit memories
US4608687A (en) * 1983-09-13 1986-08-26 International Business Machines Corporation Bit steering apparatus and method for correcting errors in stored data, storing the address of the corrected data and using the address to maintain a correct data condition
EP0173556A3 (de) * 1984-08-31 1987-05-27 Texas Instruments Incorporated Hierarchische Architektur zur Bestimmung von dem am wenigsten kürzlich benutzten Cachespeicher
JPS6246347A (ja) * 1985-08-24 1987-02-28 Hitachi Ltd 情報処理装置のエラ−処理方式
US4791642A (en) * 1986-10-17 1988-12-13 Amdahl Corporation Buffer error retry
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US4833601A (en) * 1987-05-28 1989-05-23 Bull Hn Information Systems Inc. Cache resiliency in processing a variety of address faults
DD274923A1 (de) * 1988-08-16 1990-01-03 Dresden Mikroelektronik Internes selbsttest- und redundanzprogrammierungsverfahren fuer speicherschaltkreise und anordnung zur durchfuehrung des verfahrens
US5070502A (en) * 1989-06-23 1991-12-03 Digital Equipment Corporation Defect tolerant set associative cache
US5551004A (en) * 1993-05-28 1996-08-27 Sgs-Thomson Microelectronics, Inc. Structure which renders faulty data of a cache memory uncacheable in order that a partially functional cache memory may be utilized

Also Published As

Publication number Publication date
EP0675436A1 (de) 1995-10-04
US5666482A (en) 1997-09-09
JPH0822417A (ja) 1996-01-23
DE69421379D1 (de) 1999-12-02
EP0675436B1 (de) 1999-10-27

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