SG11202109921QA - Process for transferring a useful layer to a carrier substrate - Google Patents

Process for transferring a useful layer to a carrier substrate

Info

Publication number
SG11202109921QA
SG11202109921QA SG11202109921QA SG11202109921QA SG 11202109921Q A SG11202109921Q A SG 11202109921QA SG 11202109921Q A SG11202109921Q A SG 11202109921QA SG 11202109921Q A SG11202109921Q A SG 11202109921QA
Authority
SG
Singapore
Prior art keywords
transferring
carrier substrate
useful layer
useful
layer
Prior art date
Application number
Other languages
English (en)
Inventor
Didier Landru
Oleg Kononchuk
Mohamed Nadia Ben
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of SG11202109921QA publication Critical patent/SG11202109921QA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3043—Making grooves, e.g. cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/7806—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate
SG11202109921Q 2019-03-15 2020-02-26 Process for transferring a useful layer to a carrier substrate SG11202109921QA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1902674A FR3093859B1 (fr) 2019-03-15 2019-03-15 Procédé de transfert d’une couche utile sur une substrat support
PCT/FR2020/050369 WO2020188169A1 (fr) 2019-03-15 2020-02-26 Procede de transfert d'une couche utile sur une substrat support

Publications (1)

Publication Number Publication Date
SG11202109921QA true SG11202109921QA (en) 2021-10-28

Family

ID=67384010

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11202109921Q SG11202109921QA (en) 2019-03-15 2020-02-26 Process for transferring a useful layer to a carrier substrate

Country Status (9)

Country Link
US (1) US11876015B2 (fr)
EP (1) EP3939078A1 (fr)
JP (1) JP2022527048A (fr)
KR (1) KR20210134784A (fr)
CN (1) CN113491004A (fr)
FR (1) FR3093859B1 (fr)
SG (1) SG11202109921QA (fr)
TW (1) TWI824112B (fr)
WO (1) WO2020188169A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3134229B1 (fr) * 2022-04-01 2024-03-08 Commissariat Energie Atomique Procede de transfert d’une couche mince sur un substrat support

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2861497B1 (fr) 2003-10-28 2006-02-10 Soitec Silicon On Insulator Procede de transfert catastrophique d'une couche fine apres co-implantation
FR2938120B1 (fr) * 2008-10-31 2011-04-08 Commissariat Energie Atomique Procede de formation d'une couche monocristalline dans le domaine micro-electronique
US8357974B2 (en) * 2010-06-30 2013-01-22 Corning Incorporated Semiconductor on glass substrate with stiffening layer and process of making the same
AU2013222069A1 (en) * 2012-02-26 2014-10-16 Solexel, Inc. Systems and methods for laser splitting and device layer transfer
US9257339B2 (en) * 2012-05-04 2016-02-09 Silicon Genesis Corporation Techniques for forming optoelectronic devices
FR3020175B1 (fr) * 2014-04-16 2016-05-13 Soitec Silicon On Insulator Procede de transfert d'une couche utile

Also Published As

Publication number Publication date
KR20210134784A (ko) 2021-11-10
FR3093859A1 (fr) 2020-09-18
WO2020188169A1 (fr) 2020-09-24
FR3093859B1 (fr) 2021-02-12
US11876015B2 (en) 2024-01-16
US20220157650A1 (en) 2022-05-19
CN113491004A (zh) 2021-10-08
TWI824112B (zh) 2023-12-01
EP3939078A1 (fr) 2022-01-19
TW202036784A (zh) 2020-10-01
JP2022527048A (ja) 2022-05-30

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