SG11201808956YA - Communication device and communication system - Google Patents
Communication device and communication systemInfo
- Publication number
- SG11201808956YA SG11201808956YA SG11201808956YA SG11201808956YA SG11201808956YA SG 11201808956Y A SG11201808956Y A SG 11201808956YA SG 11201808956Y A SG11201808956Y A SG 11201808956YA SG 11201808956Y A SG11201808956Y A SG 11201808956YA SG 11201808956Y A SG11201808956Y A SG 11201808956YA
- Authority
- SG
- Singapore
- Prior art keywords
- transmission
- international
- detection unit
- atsugi
- reception unit
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
- G06F11/1032—Simple parity
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/08—Arrangements for detecting or preventing errors in the information received by repeating transmission, e.g. Verdan system
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Signal Processing (AREA)
- Computer Networks & Wireless Communication (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Information Transfer Systems (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Detection And Correction Of Errors (AREA)
- Bus Control (AREA)
- Error Detection And Correction (AREA)
- Reduction Or Emphasis Of Bandwidth Of Signals (AREA)
- Stereo-Broadcasting Methods (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2016099930A JP6971538B2 (ja) | 2016-05-18 | 2016-05-18 | 通信装置、通信方法、プログラム、および、通信システム |
| PCT/JP2017/017224 WO2017199763A1 (en) | 2016-05-18 | 2017-05-02 | Communication device and communication system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| SG11201808956YA true SG11201808956YA (en) | 2018-11-29 |
Family
ID=59034818
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SG11201808956YA SG11201808956YA (en) | 2016-05-18 | 2017-05-02 | Communication device and communication system |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US10721022B2 (enExample) |
| EP (1) | EP3458962B1 (enExample) |
| JP (1) | JP6971538B2 (enExample) |
| CN (1) | CN109074294B (enExample) |
| SG (1) | SG11201808956YA (enExample) |
| TW (1) | TWI771299B (enExample) |
| WO (1) | WO2017199763A1 (enExample) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6828271B2 (ja) * | 2016-05-18 | 2021-02-10 | ソニー株式会社 | 通信装置、通信方法、プログラム、および、通信システム |
| JP6786871B2 (ja) | 2016-05-18 | 2020-11-18 | ソニー株式会社 | 通信装置、通信方法、プログラム、および、通信システム |
| CN109144913A (zh) * | 2018-09-29 | 2019-01-04 | 联想(北京)有限公司 | 一种数据处理方法、系统及电子设备 |
| US20200220571A1 (en) * | 2019-01-04 | 2020-07-09 | Qorvo Us, Inc. | Apparatus supporting multi-radio coexistence |
| US12360938B2 (en) * | 2021-03-09 | 2025-07-15 | Intel Corporation | Selection of communication protocol for management bus |
| CN116243148B (zh) * | 2023-02-22 | 2024-03-15 | 成都电科星拓科技有限公司 | 一种针对芯片i3c协议的调试和验证架构 |
Family Cites Families (32)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4621323A (en) * | 1983-03-28 | 1986-11-04 | Digital Equipment Corporation | Message transmission circuitry |
| JPS63131738A (ja) * | 1986-11-21 | 1988-06-03 | Hitachi Seiko Ltd | パリテイチエツク方式 |
| JPH06161793A (ja) * | 1992-11-18 | 1994-06-10 | Fujitsu Ltd | パリティエラ発生時の対処装置 |
| US5465262A (en) * | 1994-01-28 | 1995-11-07 | International Business Machines Corporation | Method and structure for providing error correction code and automatic parity sensing |
| US5453999A (en) * | 1994-04-26 | 1995-09-26 | Unisys Corporation | Address verification system using parity for transmitting and receiving circuits |
| US5566193A (en) * | 1994-12-30 | 1996-10-15 | Lucent Technologies Inc. | Method and apparatus for detecting and preventing the communication of bit errors on a high performance serial data link |
| US5835511A (en) * | 1996-05-17 | 1998-11-10 | Advanced Micro Devices, Inc. | Method and mechanism for checking integrity of byte enable signals |
| JPH10334044A (ja) * | 1997-06-03 | 1998-12-18 | Oki Electric Ind Co Ltd | シリアルインタフェース方法 |
| US6356984B1 (en) | 1998-06-30 | 2002-03-12 | Sun Microsystems, Inc. | Digital data processing system having a data bus and a control bus |
| JP4047498B2 (ja) * | 1999-08-25 | 2008-02-13 | 株式会社東芝 | データ処理装置 |
| US6874052B1 (en) | 2000-09-29 | 2005-03-29 | Lucent Technologies Inc. | Expansion bridge apparatus and method for an I2C bus |
| US6543023B2 (en) * | 2001-02-05 | 2003-04-01 | Agere Systems Inc. | Parity-check coding for efficient processing of decoder error events in data storage, communication and other systems |
| AU2003225172A1 (en) * | 2002-05-08 | 2003-11-11 | Semtech Corporation | Single-wire communication bus for miniature low-power systems |
| JP2005084791A (ja) * | 2003-09-05 | 2005-03-31 | Alpine Electronics Inc | データ通信方法 |
| US7356681B2 (en) * | 2004-03-05 | 2008-04-08 | Finisar Corporation | Transient transceiver clock configuration |
| US7325155B2 (en) * | 2004-09-14 | 2008-01-29 | Seagate Technology Llc | Embedded system with reduced susceptibility to single event upset effects |
| US7634694B2 (en) * | 2004-10-15 | 2009-12-15 | Standard Microsystems Corporation | Selective scrambler for use in a communication system and method to minimize bit error at the receiver |
| US7478286B2 (en) * | 2005-04-08 | 2009-01-13 | Linear Technology Corporation | Circuit and method of detecting and resolving stuck I2C buses |
| US7596743B2 (en) * | 2005-09-28 | 2009-09-29 | Ati Technologies Inc. | Method and apparatus for error management |
| US20070113162A1 (en) * | 2005-10-26 | 2007-05-17 | Lery Scott A | Error code for wireless remote control device and method |
| CN100458722C (zh) * | 2005-12-12 | 2009-02-04 | 深圳艾科创新微电子有限公司 | 一种通过pc对i2c接口器件进行调试的系统及方法 |
| US7694211B2 (en) * | 2006-08-21 | 2010-04-06 | Agere Systems, Inc. | Method and apparatus for error compensation |
| JP5507813B2 (ja) * | 2007-02-16 | 2014-05-28 | パナソニック株式会社 | 送信装置及び受信装置 |
| US7865805B1 (en) * | 2007-02-26 | 2011-01-04 | Lockheed Martin Corporation | Multiple bit upset insensitive error detection and correction circuit for field programmable gate array based on static random access memory blocks |
| JP5354979B2 (ja) * | 2007-07-12 | 2013-11-27 | パナソニック株式会社 | 低密度パリティ検査畳み込み符号(ldpc−cc)符号化器及びldpc−cc復号器 |
| US20100268897A1 (en) * | 2009-04-16 | 2010-10-21 | Keishi Okamoto | Memory device and memory device controller |
| US8239745B2 (en) * | 2009-06-02 | 2012-08-07 | Freescale Semiconductor, Inc. | Parity data encoder for serial communication |
| JP5724877B2 (ja) * | 2009-10-21 | 2015-05-27 | 日本電気株式会社 | パリティ制御システム及び方法、並びに通信システム及び方法 |
| US8194480B2 (en) * | 2009-11-19 | 2012-06-05 | Himax Technologies Limited | Method for initializing memory device |
| US9389953B2 (en) * | 2013-03-04 | 2016-07-12 | Samsung Electronics Co., Ltd. | Semiconductor memory device and system conducting parity check and operating method of semiconductor memory device |
| US9658921B2 (en) * | 2013-10-31 | 2017-05-23 | Samsung Display Co., Ltd. | Maximal transition hamming codes |
| US10007628B2 (en) * | 2014-06-18 | 2018-06-26 | Qualcomm Incorporated | Dynamically adjustable multi-line bus shared by multi-protocol devices |
-
2016
- 2016-05-18 JP JP2016099930A patent/JP6971538B2/ja active Active
-
2017
- 2017-05-02 CN CN201780029045.3A patent/CN109074294B/zh active Active
- 2017-05-02 SG SG11201808956YA patent/SG11201808956YA/en unknown
- 2017-05-02 EP EP17729204.2A patent/EP3458962B1/en active Active
- 2017-05-02 WO PCT/JP2017/017224 patent/WO2017199763A1/en not_active Ceased
- 2017-05-02 US US16/099,306 patent/US10721022B2/en active Active
- 2017-05-05 TW TW106114886A patent/TWI771299B/zh active
Also Published As
| Publication number | Publication date |
|---|---|
| CN109074294A (zh) | 2018-12-21 |
| US10721022B2 (en) | 2020-07-21 |
| EP3458962B1 (en) | 2021-04-14 |
| EP3458962A1 (en) | 2019-03-27 |
| TW201741891A (zh) | 2017-12-01 |
| TWI771299B (zh) | 2022-07-21 |
| JP6971538B2 (ja) | 2021-11-24 |
| WO2017199763A1 (en) | 2017-11-23 |
| JP2017208710A (ja) | 2017-11-24 |
| CN109074294B (zh) | 2023-03-10 |
| US20190215100A1 (en) | 2019-07-11 |
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