SG11201506674RA - Data processing device and control method therefor - Google Patents

Data processing device and control method therefor

Info

Publication number
SG11201506674RA
SG11201506674RA SG11201506674RA SG11201506674RA SG11201506674RA SG 11201506674R A SG11201506674R A SG 11201506674RA SG 11201506674R A SG11201506674R A SG 11201506674RA SG 11201506674R A SG11201506674R A SG 11201506674RA SG 11201506674R A SG11201506674R A SG 11201506674RA
Authority
SG
Singapore
Prior art keywords
data processing
processing device
control method
method therefor
therefor
Prior art date
Application number
SG11201506674RA
Other languages
English (en)
Inventor
Tomoyoshi Sato
Original Assignee
Atonarp Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atonarp Inc filed Critical Atonarp Inc
Publication of SG11201506674RA publication Critical patent/SG11201506674RA/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/1776—Structural details of configuration resources for memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H03K19/17744—Structural details of routing resources for input/output signals

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Logic Circuits (AREA)
  • Stored Programmes (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • General Physics & Mathematics (AREA)
SG11201506674RA 2013-03-01 2014-03-03 Data processing device and control method therefor SG11201506674RA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013040536 2013-03-01
PCT/JP2014/001129 WO2014132669A1 (ja) 2013-03-01 2014-03-03 データ処理装置およびその制御方法

Publications (1)

Publication Number Publication Date
SG11201506674RA true SG11201506674RA (en) 2015-09-29

Family

ID=51427943

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201506674RA SG11201506674RA (en) 2013-03-01 2014-03-03 Data processing device and control method therefor

Country Status (11)

Country Link
US (3) US9667256B2 (ja)
EP (1) EP2963824B1 (ja)
JP (2) JP6290855B2 (ja)
KR (1) KR20150127608A (ja)
CN (1) CN105027446B (ja)
AU (1) AU2014222148A1 (ja)
CA (1) CA2901062A1 (ja)
EA (1) EA201591613A1 (ja)
IL (1) IL240911A0 (ja)
SG (1) SG11201506674RA (ja)
WO (1) WO2014132669A1 (ja)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107478710A (zh) * 2017-09-14 2017-12-15 安徽理工大学 一种消除Hadamard离子迁移谱基线漂移失真方法
US11360930B2 (en) 2017-12-19 2022-06-14 Samsung Electronics Co., Ltd. Neural processing accelerator
JP7080065B2 (ja) * 2018-02-08 2022-06-03 株式会社Ｓｃｒｅｅｎホールディングス データ処理方法、データ処理装置、データ処理システム、およびデータ処理プログラム
WO2021090711A1 (ja) * 2019-11-06 2021-05-14 太陽誘電株式会社 データ処理装置および情報処理装置

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5850564A (en) * 1995-05-03 1998-12-15 Btr, Inc, Scalable multiple level tab oriented interconnect architecture
GB2305759A (en) * 1995-09-30 1997-04-16 Pilkington Micro Electronics Semi-conductor integrated circuit
US5963050A (en) * 1997-02-26 1999-10-05 Xilinx, Inc. Configurable logic element with fast feedback paths
US6020760A (en) 1997-07-16 2000-02-01 Altera Corporation I/O buffer circuit with pin multiplexing
US6678646B1 (en) * 1999-12-14 2004-01-13 Atmel Corporation Method for implementing a physical design for a dynamically reconfigurable logic circuit
TWI234737B (en) * 2001-05-24 2005-06-21 Ip Flex Inc Integrated circuit device
EP1416388A4 (en) * 2001-07-12 2006-02-08 Ip Flex Inc INTEGRATED CIRCUIT DEVICE
CA2459411C (en) * 2001-09-07 2013-04-02 Ip Flex Inc. Data processing system and control method
JP4572835B2 (ja) * 2003-08-29 2010-11-04 富士ゼロックス株式会社 データ処理装置
EP1780644A4 (en) * 2004-07-30 2007-11-21 Fujitsu Ltd CONVERTIBLE CIRCUIT AND CONTROL PROCEDURE OF A CONVERTIBLE CIRCUIT
ATE458309T1 (de) 2004-10-28 2010-03-15 Ip Flex Inc Datenverarbeitungsgerät mit rekonfigurierbarer logischer schaltung
US7493426B2 (en) * 2005-01-31 2009-02-17 International Business Machines Corporation Data communication method and apparatus utilizing programmable channels for allocation of buffer space and transaction control
US7268581B1 (en) * 2005-04-21 2007-09-11 Xilinx, Inc. FPGA with time-multiplexed interconnect
JP2007041796A (ja) * 2005-08-02 2007-02-15 Mitsubishi Electric Corp コード生成装置
US7486111B2 (en) 2006-03-08 2009-02-03 Tier Logic, Inc. Programmable logic devices comprising time multiplexed programmable interconnect
WO2007149495A2 (en) 2006-06-21 2007-12-27 Element Cxi, Llc Program binding system, method and software for a resilient integrated circuit architecture
DE102006032650B3 (de) * 2006-07-13 2007-09-06 Technotrans Ag Farbversorgungsvorrichtung für eine Druckmaschine
US8136076B2 (en) * 2006-08-31 2012-03-13 Fuji Xerox Co., Ltd. Method and system for mounting circuit design on reconfigurable device
US7500023B2 (en) * 2006-10-10 2009-03-03 International Business Machines Corporation Facilitating input/output processing by using transport control words to reduce input/output communications
JP5014899B2 (ja) * 2007-07-02 2012-08-29 ルネサスエレクトロニクス株式会社 再構成可能デバイス
JP5251171B2 (ja) 2008-03-06 2013-07-31 富士通セミコンダクター株式会社 論理回路装置
DE102011121159A1 (de) * 2011-12-15 2013-06-20 Olympus Winter & Ibe Gmbh Resektoskop mit einem Schaft

Also Published As

Publication number Publication date
IL240911A0 (en) 2015-10-29
CA2901062A1 (en) 2014-09-04
JP6656217B2 (ja) 2020-03-04
US20180294814A1 (en) 2018-10-11
US20160020771A1 (en) 2016-01-21
EP2963824A4 (en) 2016-10-19
US9667256B2 (en) 2017-05-30
JP6290855B2 (ja) 2018-03-07
EP2963824B1 (en) 2020-08-19
US20170257102A1 (en) 2017-09-07
JP2018029377A (ja) 2018-02-22
AU2014222148A1 (en) 2015-09-17
WO2014132669A1 (ja) 2014-09-04
EP2963824A1 (en) 2016-01-06
CN105027446B (zh) 2019-06-21
JPWO2014132669A1 (ja) 2017-02-02
CN105027446A (zh) 2015-11-04
EA201591613A1 (ru) 2016-05-31
US10009031B2 (en) 2018-06-26
KR20150127608A (ko) 2015-11-17

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