SG10201900899UA - Semiconductor Memory Devices - Google Patents
Semiconductor Memory DevicesInfo
- Publication number
- SG10201900899UA SG10201900899UA SG10201900899UA SG10201900899UA SG10201900899UA SG 10201900899U A SG10201900899U A SG 10201900899UA SG 10201900899U A SG10201900899U A SG 10201900899UA SG 10201900899U A SG10201900899U A SG 10201900899UA SG 10201900899U A SG10201900899U A SG 10201900899UA
- Authority
- SG
- Singapore
- Prior art keywords
- memory devices
- semiconductor memory
- stacks
- gate electrode
- conductive
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
Abstract
Semiconductor memory devices may include first and second stacks on a substrate and first and second interconnection lines on the first and second stacks. Each of the first and second stacks may include semiconductor patterns vertically stacked on the substrate, conductive lines connected to the semiconductor patterns, respectively, and a gate electrode that is adjacent to the semiconductor patterns and extends in a vertical direction. The first stack may include a first conductive line and a first gate electrode, and the second stack may include a second conductive line and a second gate electrode. Lower surfaces of the first and second conductive lines may be coplanar. The first interconnection line may be electrically connected to at least one of the first and second conductive lines. The second interconnection line may be electrically connected to at least one of the first and second gate electrodes. FIG. 5
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201862629335P | 2018-02-12 | 2018-02-12 | |
| KR1020180058523A KR102494114B1 (en) | 2018-02-12 | 2018-05-23 | Semiconductor memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| SG10201900899UA true SG10201900899UA (en) | 2019-09-27 |
Family
ID=67808335
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SG10201900899UA SG10201900899UA (en) | 2018-02-12 | 2019-01-31 | Semiconductor Memory Devices |
Country Status (2)
| Country | Link |
|---|---|
| KR (1) | KR102494114B1 (en) |
| SG (1) | SG10201900899UA (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20210056778A (en) | 2019-11-11 | 2021-05-20 | 삼성전자주식회사 | Integrated circuit device and method of manufacturing the same |
| CN116367540B (en) * | 2023-05-10 | 2023-10-24 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof |
-
2018
- 2018-05-23 KR KR1020180058523A patent/KR102494114B1/en active IP Right Grant
-
2019
- 2019-01-31 SG SG10201900899UA patent/SG10201900899UA/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| KR102494114B1 (en) | 2023-02-01 |
| KR20190098007A (en) | 2019-08-21 |
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