KR102494114B1 - Semiconductor memory device - Google Patents

Abstract

The present invention relates to a semiconductor device, and more particularly, to a first laminated structure and a second laminated structure on a substrate; and a first wiring and a second wiring on the first and second laminated structures. Each of the first and second stacked structures may include: vertically stacked semiconductor patterns; conductive lines connected to the semiconductor patterns and extending horizontally; and a gate electrode extending vertically adjacent to the semiconductor patterns. The conductive lines of the first stacked structure include a first conductive line, the conductive lines of the second stacked structure include a second conductive line positioned at the same level as the first conductive line, A wiring is electrically connected to at least one of the first and second conductive lines, and the second wiring is electrically connected to at least one of the gate electrodes of the first and second stacked structures.

Description

Semiconductor memory device

The present invention relates to a semiconductor device, and more particularly, to a three-dimensional semiconductor memory device having an improved degree of integration.

It is required to increase the degree of integration of semiconductor devices in order to meet the excellent performance and low price demanded by consumers. In the case of a semiconductor device, since the degree of integration is an important factor in determining the price of a product, an increased degree of integration is particularly required. In the case of a conventional two-dimensional or planar semiconductor device, since the degree of integration is mainly determined by the area occupied by a unit memory cell, it is greatly affected by the level of fine pattern formation technology. However, since ultra-expensive equipment is required for miniaturization of the pattern, although the degree of integration of 2D semiconductor devices is increasing, it is still limited. Accordingly, three-dimensional semiconductor memory devices having three-dimensionally arranged memory cells have been proposed.

An object to be solved by the present invention is to provide a three-dimensional semiconductor memory device with improved integration.

According to the concept of the present invention, a semiconductor memory device includes a first stacked structure and a second stacked structure on a substrate; and a first wire and a second wire on the first and second stacked structures. Each of the first and second stacked structures may include: vertically stacked semiconductor patterns; conductive lines connected to the semiconductor patterns and extending horizontally; and a gate electrode extending vertically adjacent to the semiconductor patterns. The conductive lines of the first stacked structure include a first conductive line, the conductive lines of the second stacked structure include a second conductive line positioned at the same level as the first conductive line, A wire may be electrically connected to at least one of the first and second conductive lines, and the second wire may be electrically connected to at least one of the gate electrodes of the first and second stacked structures.

According to another concept of the present invention, a semiconductor memory device includes a substrate including a cell region and a contact region; semiconductor patterns stacked vertically on the cell region, each of the semiconductor patterns including a first impurity region, a second impurity region, and a channel region between the first and second impurity regions; first conductive lines connected to the first impurity regions of the semiconductor patterns, the first conductive lines extending horizontally from the cell region to the contact region; capacitors connected to the second impurity regions of the semiconductor patterns; and contacts contacting the first conductive lines on the contact area. The contacts may include a first contact and a second contact closer to the cell region than the first contact, and a level of a bottom surface of the second contact may be higher than a level of a bottom surface of the first contact. .

According to another concept of the present invention, a semiconductor memory device includes a first stacked structure and a second stacked structure on a substrate; and a first wire and a second wire on the first and second stacked structures. The first wire extends in a first direction, the second wire extends in a second direction crossing the first direction, and each of the first and second stacked structures includes: a three-dimensionally arranged memory cell transistors; a bit line connected to the horizontally arranged memory cell transistors; and a word line connected to the vertically arranged memory cell transistors. On the contact area, the first wire is electrically connected to at least one of the bit lines of the first and second stacked structures, and on the cell area, the second wire is connected to the first and second stacked structures. may be electrically connected to at least one of the word lines of

In a 3D semiconductor memory device according to embodiments of the present invention, memory cells may be three-dimensionally arranged on a substrate. Bit lines and word lines may be efficiently connected to peripheral circuit areas through wires on memory cells.

1 is a simplified circuit diagram illustrating a cell array of a 3D semiconductor memory device according to example embodiments.
2 is a perspective view illustrating a 3D semiconductor memory device according to example embodiments.
3A, 3B, and 3C are cross-sectional views taken along lines A-A', B-B', and C-C' of FIG. 2, respectively.
FIG. 3D is an enlarged cross-sectional view of area M of FIG. 3A.
FIG. 4 is a cross-sectional view taken along the line A-A′ of FIG. 2 for explaining a 3D semiconductor memory device according to an exemplary embodiment of the present invention.
5 is a perspective view illustrating a 3D semiconductor memory device according to example embodiments.
6A is a cross-sectional view along lines A-A' and B-B' of FIG. 5;
FIG. 6B is a cross-sectional view taken along line C-C′ of FIG. 5 .
7A is a cross-sectional view taken along lines A-A' and B-B' of FIG. 5;
FIG. 7B is a cross-sectional view taken along line C-C′ of FIG. 5 .
8A is a cross-sectional view taken along lines A-A' and B-B' of FIG. 5;
FIG. 8B is a cross-sectional view taken along line C-C′ of FIG. 5 .
9 is a cross-sectional view taken along line C-C′ of FIG. 5;
10 is a cross-sectional view along lines A-A' and B-B' of FIG. 5;
11 is a perspective view illustrating a 3D semiconductor memory device according to example embodiments.
FIG. 12 is a cross-sectional view taken along line A-A' of FIG. 5 .
13 is a perspective view illustrating a 3D semiconductor memory device according to example embodiments.
14 is a perspective view illustrating a 3D semiconductor memory device according to example embodiments.
15 is a perspective view illustrating a 3D semiconductor memory device according to example embodiments.
16 is a cross-sectional view taken along the line A-A' of FIG. 15;
17 is a perspective view illustrating a 3D semiconductor memory device according to example embodiments.
18 is a cross-sectional view along lines A-A' and B-B' of FIG. 17;

1 is a simplified circuit diagram illustrating a cell array of a 3D semiconductor memory device according to example embodiments.

Referring to FIG. 1 , a cell array of a 3D semiconductor memory device according to example embodiments may include a plurality of sub-cell arrays (SCA). The sub cell arrays SCA may be arranged along the second direction D2.

Each of the sub cell arrays SCA may include a plurality of bit lines BL, a plurality of word lines WL, and a plurality of memory cell transistors MCT. One memory cell transistor MCT may be disposed between one word line WL and one bit line BL.

The bit lines BL may be conductive patterns (eg, metal lines) spaced apart from the substrate and disposed on the substrate. The bit lines BL may extend in the first direction D1. The bit lines BL in one sub-cell array SCA may be spaced apart from each other in a vertical direction (ie, in the third direction D3).

The word lines WL may be conductive patterns (eg, metal lines) extending from the substrate in a direction perpendicular to the substrate (eg, in the third direction D3 ). The word lines WL in one sub-cell array SCA may be spaced apart from each other in the first direction D1.

A gate of the memory cell transistor MCT may be connected to the word line WL, and a source of the memory cell transistor MCT may be connected to the bit line BL. Each of the memory cell transistors MCT may include an information storage element DS. For example, the information storage element DS may be a capacitor, and a drain of the memory cell transistor MCT may be connected to a first electrode of the capacitor. A second electrode of the capacitor may be connected to a ground wire PP.

2 is a perspective view illustrating a 3D semiconductor memory device according to example embodiments. 3A, 3B, and 3C are cross-sectional views taken along lines A-A', B-B', and C-C' of FIG. 2, respectively. FIG. 3D is an enlarged cross-sectional view of area M of FIG. 3A.

Referring to FIGS. 1, 2, and 3A to 3D , a substrate 100 including a cell region CAR and a contact region CTR may be provided. A first interlayer insulating layer ILD1 may be provided on the substrate 100 . The substrate 100 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate.

First to fourth stacked structures SS1 to SS4 may be provided on the substrate 100 . The first to fourth stacked structures SS1 - SS4 may be vertically spaced apart from the substrate 100 with the first interlayer insulating layer ILD1 interposed therebetween. The first to fourth stacked structures SS1 to SS4 may extend parallel to each other in the first direction D1. The first to fourth stacked structures SS1 to SS4 may be arranged along the second direction D2. Each of the first to fourth stacked structures SS1 to SS4 may include the sub cell array SCA described above with reference to FIG. 1 .

Each of the first to fourth stacked structures SS1 - SS4 may include semiconductor patterns SP and insulating layers IL alternately stacked on the first interlayer insulating layer ILD1 . The vertically stacked semiconductor patterns SP may be vertically spaced apart from each other by insulating layers IL. An insulating layer IL may be interposed between a pair of vertically adjacent semiconductor patterns SP. The insulating layers IL may be selected from the group consisting of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer containing carbon, a silicon nitride layer containing carbon, and a silicon oxynitride layer containing carbon.

Each of the semiconductor patterns SP may have a line shape, a bar shape, or a column shape extending in the second direction D2 . For example, the semiconductor patterns SP may include silicon, germanium, silicon-germanium, or indium gallium zinc oxide (IGZO). Each of the semiconductor patterns SP may include a first impurity region SD1 , a second impurity region SD2 , and a channel region CH.

The channel region CH may be disposed between the first and second impurity regions SD1 and SD2. The first and second impurity regions SD1 and SD2 may have a first conductivity type (eg, n-type). The channel region CH may be undoped or may have a second conductivity type (eg, p-type) different from the first conductivity type.

The channel region CH may correspond to a channel of the memory cell transistor MCT of FIG. 1 . The first and second impurity regions SD1 and SD2 may respectively correspond to the source and drain of the memory cell transistor MCT of FIG. 1 .

The semiconductor patterns SP may be provided on the cell region CAR of the substrate 100 . Each of the first to fourth stacked structures SS1 to SS4 may include semiconductor patterns SP of first to fourth columns R1 to R4 . Each of the first to fourth columns R1 to R4 may include semiconductor patterns SP that are vertically stacked and overlap each other. For example, the number of semiconductor patterns SP in each of the first to fourth columns R1 to R4 is 6, but is not particularly limited thereto. The first to fourth columns R1 to R4 may be spaced apart from each other and arranged along the first direction D1.

Each of the first to fourth stacked structures SS1 - SS4 may further include vertically stacked first conductive lines CL1 . The vertically stacked first conductive lines CL1 may be vertically spaced apart from each other by insulating layers IL. An insulating layer IL may be interposed between a pair of vertically adjacent first conductive lines CL1 .

The first conductive lines CL1 may have a line shape or a bar shape extending in the first direction D1 . The first conductive lines CL1 may extend from the cell region CAR of the substrate 100 to the contact region CTR.

Each of the first conductive lines CL1 may directly contact the semiconductor patterns SP. For example, each of the first conductive lines CL1 may be positioned at substantially the same level as the semiconductor patterns SP. Each of the first conductive lines CL1 may be connected to the first impurity regions SD1 of the semiconductor patterns SP. The semiconductor patterns SP of the first to fourth columns R1 to R4 positioned at the same level as each of the first conductive lines CL1 may extend in the second direction D2.

Referring to FIG. 3C , each of the first to fourth stacked structures SS1 to SS4 on the contact region CTR of the substrate 100 may have a stepped structure. The length of the first conductive lines CL1 stacked on the contact region CTR in the first direction D1 may decrease as the distance from the upper surface of the substrate 100 increases. For example, the length of the lowermost first conductive line CL1 among the stacked first conductive lines CL1 may be longer than that of each of the remaining first conductive lines CL1. A length of an uppermost first conductive line CL1 among the stacked first conductive lines CL1 may be shorter than a length of each of the remaining first conductive lines CL1 .

The first conductive lines CL1 may include a conductive material. For example, the conductive material may include a doped semiconductor material (doped silicon, doped germanium, etc.), a conductive metal nitride (titanium nitride, tantalum nitride, etc.), a metal (tungsten, titanium, tantalum, etc.), and a metal-semiconductor compound (tungsten silicide, cobalt silicide, titanium silicide, etc.). The first conductive lines CL1 may be the bit lines BL described with reference to FIG. 1 .

Each of the first to fourth stacked structures SS1 to SS4 may further include vertically stacked information storage elements DS. The vertically stacked information storage elements DS may be vertically spaced apart from each other by insulating layers IL. Each of the information storage elements DS may extend in the second direction D2 from each of the semiconductor patterns SP.

Each of the information storage elements DS may directly contact each of the semiconductor patterns SP. For example, each of the information storage elements DS may be located at substantially the same level as each of the semiconductor patterns SP. Each of the information storage elements DS may be connected to the second impurity region SD2 of each of the semiconductor patterns SP.

Referring to FIG. 3D , each of the information storage elements DS may include a first electrode EL1 , a dielectric layer DL, and a second electrode EL2 . In other words, the information storage element DS according to embodiments of the present invention may be a capacitor.

The first electrode EL1 may be directly connected to the second impurity region SD2 of the semiconductor pattern SP. The first electrode EL1 may have a hollow cylinder shape. The first electrode EL1 may include at least one of a metal material, a metal nitride film, and a metal silicide. For example, the first electrode EL1 may include a high melting point metal layer such as cobalt, titanium, nickel, tungsten, or molybdenum. The first electrode EL1 may include a metal nitride layer such as a titanium nitride layer, a titanium silicon nitride layer, a titanium aluminum nitride layer, a tantalum nitride layer, a tantalum silicon nitride layer, a tantalum aluminum nitride layer, and a tungsten nitride layer.

The dielectric layer DL may be interposed between the first electrode EL1 and the second electrode EL2. The dielectric layer DL may directly cover the inner wall of the first electrode EL1. For example, the dielectric layer DL may include metal oxides such as hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, tantalum oxide, and titanium oxide, and SrTiO3(STO), (Ba,Sr)TiO3(BST), BaTiO3, PZT, It may include at least one of dielectric materials having a perovskite structure, such as PLZT.

The second electrode EL2 may be provided on the dielectric layer DL. The second electrode EL2 may fill the inside of the cylindrical first electrode EL1. The second electrode EL2 may be connected to a third conductive line CL3 to be described later. The second electrode EL2 may include at least one of impurity-doped silicon, a metal material, a metal nitride film, and a metal silicide. For example, the second electrode EL2 may include substantially the same material as the first electrode EL1.

Second conductive lines CL2 passing through the first to fourth stacked structures SS1 to SS4 may be provided on the cell region CAR of the substrate 100 . The second conductive lines CL2 may have a columnar shape or a bar shape extending in a direction perpendicular to the upper surface of the substrate 100 (ie, in the third direction D3 ). The second conductive lines CL2 of each of the first to fourth stacked structures SS1 to SS4 may be arranged in the first direction D1. The second conductive lines CL2 may be disposed adjacent to the first to fourth columns R1 to R4 of the semiconductor patterns SP, respectively.

For example, the first second conductive line CL2 penetrating the third stacked structure SS3 may be adjacent to sidewalls of the semiconductor patterns SP of the first column R1 . The first and second conductive lines CL2 may extend vertically on sidewalls of the semiconductor patterns SP of the first column R1 . The second conductive line CL2 penetrating the third stacked structure SS3 may be adjacent to sidewalls of the semiconductor patterns SP of the second column R2 . The second conductive line CL2 may extend vertically on sidewalls of the semiconductor patterns SP in the second column R2 . A vertical insulating pattern VIP may be interposed between the first second conductive line CL2 and the semiconductor patterns SP of the second column R2. The vertical insulating pattern VIP may include a silicon oxide layer.

Each of the second conductive lines CL2 may be disposed on the channel regions CH of the semiconductor patterns SP adjacent thereto. The second conductive lines CL2 may be gate electrodes. In other words, the second conductive lines CL2 may be gates of the memory cell transistors MCT of FIG. 1 . A gate insulating layer GI may be disposed between the second conductive line CL2 and the channel regions CH of the semiconductor patterns SP. The gate insulating layer GI may include a single layer selected from among a high dielectric layer, a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer, or a combination thereof. For example, the high dielectric layer may include hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, and lead. It may include at least one of scandium tantalum oxide and lead zinc niobate.

The second conductive lines CL2 may include a conductive material, and the conductive material may be any one of a doped semiconductor material, a conductive metal nitride, a metal, and a metal-semiconductor compound. The second conductive lines CL2 may be the word lines WL described with reference to FIG. 1 .

Third conductive lines CL3 extending in the first direction D1 in parallel with the first to fourth stacked structures SS1 to SS4 may be provided on the cell region CAR of the substrate 100 . there is. The first third conductive line CL3 may be disposed between the first and second stacked structures SS1 and SS2, and the second third conductive line CL3 may be disposed between the third and fourth stacked structures SS3. , SS4).

The third conductive lines CL3 may be directly connected to the second electrode EL2 of the information storage element DS described above with reference to FIG. 3D. The first third conductive line CL3 may be connected in common to the second electrodes EL2 of the capacitors of the first and second stacked structures SS1 and SS2, and the second third conductive line CL3 may be The second electrodes EL2 of the capacitors of the third and fourth stacked structures SS3 and SS4 may be connected in common.

The third conductive lines CL3 may include a conductive material, and the conductive material may be any one of a doped semiconductor material, a conductive metal nitride, a metal, and a metal-semiconductor compound. The third conductive lines CL3 may be the ground wires PP described with reference to FIG. 1 .

A second interlayer insulating layer ILD2 covering the first to fourth stacked structures SS1 - SS4 may be provided on the first interlayer insulating layer ILD1 . Each of the first and second interlayer insulating layers ILD1 and ILD2 may include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

In one embodiment of the present invention, the first and second stacked structures SS1 and SS2 and the third and fourth stacked structures SS3 and SS4 may have substantially the same structure as each other. The first and second stacked structures SS1 and SS2 and the third and fourth stacked structures SS3 and SS4 may be symmetrical to each other. The first and second stacked structures SS1 and SS2 may be mirror symmetrical to each other with respect to the third conductive line CL3. The third and fourth stacked structures SS3 and SS4 may be mirror symmetrical to each other with respect to the third conductive line CL3 . The second and third stacked structures SS2 and SS3 may be mirror symmetrical to each other based on the second interlayer insulating layer ILD2 filled therebetween.

FIG. 4 is a cross-sectional view taken along the line A-A′ of FIG. 2 for explaining a 3D semiconductor memory device according to an exemplary embodiment of the present invention. In this embodiment, detailed descriptions of technical features overlapping with those previously described with reference to FIGS. 1, 2, and 3A to 3D will be omitted, and differences will be described in detail.

Referring to FIG. 4 , each of the semiconductor patterns SP may further include an end layer (SG) interposed between the first conductive line CL1 and the first impurity region SD1. For example, the end film SG may be a region of the semiconductor pattern SP. As another example, the end film SG may be a film additionally formed between the semiconductor pattern SP and the first conductive line CL1.

The end film SG may include a semiconductor element having a relatively narrow band gap. When the semiconductor pattern SP includes silicon, the end layer SG may further include germanium. For example, the first and second impurity regions SD1 and SD2 and the channel region CH of the semiconductor pattern SP may include silicon, and the end film SG may include silicon-germanium. there is.

A silicide layer SC may be interposed between the first conductive line CL1 and the end layer SG. The silicide layer SC may include a metal-semiconductor compound (tungsten silicide, cobalt silicide, titanium silicide, etc.).

In an embodiment, forming the end film SG is a semiconductor having a narrow band gap by performing plasma-assisted doping (PLAD) on the first impurity region SD1 of the semiconductor pattern SP. This may include doping a portion of the first impurity region SD1 with an element (eg, germanium). After forming the end film SG, the silicide film SC may be formed by performing a metal-silicide process. After forming the silicide layer SC, the first conductive line CL1 may be formed.

During operation of the memory device, holes may be accumulated in the semiconductor pattern SP due to a floating body effect. Accumulated holes may recombine with electrons of a capacitor of a memory cell, and thus data of the capacitor may be lost.

In this embodiment, the end film SG may have a narrower band gap than the first and second impurity regions SD1 and SD2 and the channel region CH. The end layer SG may remove a hole barrier so that holes accumulated in the semiconductor pattern SP can escape through the first conductive line CL1. As a result, the semiconductor memory device according to the present exemplary embodiment may remove accumulated holes through the first conductive line CL1 by additionally including the end film SG.

5 is a perspective view illustrating a 3D semiconductor memory device according to example embodiments. 6A is a cross-sectional view along lines A-A' and B-B' of FIG. 5; FIG. 6B is a cross-sectional view taken along line C-C′ of FIG. 5 . In this embodiment, detailed descriptions of technical features overlapping with those previously described with reference to FIGS. 1, 2, and 3A to 3D will be omitted, and differences will be described in detail.

Referring to FIGS. 5, 6A, and 6B , the substrate 100 may include a cell area CAR, a contact area CTR, a first peripheral circuit area PER1 and second peripheral circuit areas PER2. can The contact region CTR may be interposed between the cell region CAR and the first peripheral circuit region PER1.

The first and second peripheral circuit regions PER1 and PER2 may include peripheral transistors, resistors, and capacitors electrically connected to the memory cell arrays. For example, the first peripheral circuit area PER1 may include sense amplifiers connected to the bit lines BL of the cell area CAR. The second peripheral circuit regions PER2 may include row decoders and/or sub-word line drivers connected to the word lines WL of the cell region CAR. can

Referring to FIG. 6A , a device isolation layer ST defining an active region ACT may be provided on the first peripheral circuit region PER1 of the substrate 100 . A peripheral gate electrode PG may be provided on the active region ACT to cross the active region ACT. Source/drain regions IR may be provided on the active region ACT on both sides of the peripheral gate electrode PG. A peripheral gate insulating layer PGI may be interposed between the peripheral gate electrode PG and the active region ACT. A gate capping layer PGP may be provided on the peripheral gate electrode PG. A pair of spacers PSP may be provided on both sidewalls of the peripheral gate electrode PG. A first interlayer insulating layer ILD1 may cover the active region ACT, the spacers PSP, and the gate capping layer PGP.

A lower interconnection LML extending in a direction toward the cell region CAR may be provided on the first interlayer insulating layer ILD1 . The lower interconnection LML may be electrically connected to the source/drain region IR of the active region ACT through the lower contact LCNT penetrating the first interlayer insulating layer ILD1. Although not shown, the lower wiring LML may be electrically connected to the peripheral gate electrode PG through a lower contact LCNT penetrating the first interlayer insulating layer ILD1 and the gate capping layer PGP.

Structures of peripheral transistors on the second peripheral circuit regions PER2 may be substantially the same as structures of peripheral transistors on the first peripheral circuit region PER1 shown in FIG. 6A .

First to fourth stacked structures SS1 to SS4 may be provided on the cell region CAR and the contact region CTR of the substrate 100 . The first to fourth stacked structures SS1 - SS4 may be provided on the first interlayer insulating layer ILD1. The first to fourth stacked structures SS1 - SS4 may be positioned at a higher level than the peripheral transistors of the first and second peripheral circuit regions PER1 and PER2 . For simplicity of drawing, the first to fourth stacked structures SS1 to SS4 are illustrated while omitting the semiconductor patterns SP described above in FIG. 2 .

Contacts CNT passing through the second interlayer insulating layer ILD2 covering the first to fourth stacked structures SS1 - SS4 and contacting the first conductive lines CL1 on the contact region CTR are provided. It can be. Contacts CNT may be provided to pass through the second interlayer insulating layer ILD2 on the first and second peripheral circuit regions PER1 and PER2 and contact the lower wires LML.

The contacts CNT contacting the first conductive lines CL1 of the contact region CTR may be arranged in the first direction D1. The contacts CNT of the contact region CTR may be disposed on a stepped structure of each of the first to fourth stacked structures SS1 to SS4 . Accordingly, the bottom surfaces of the contacts CNT of the contact region CTR may increase in level as they approach the cell region CAR. For example, the bottom surface of the contact CNT close to the first peripheral circuit area PER1 may be located at the first level LEV1, and the bottom surface of the contact CNT close to the cell area CAR may be located at the first level LEV1. It may be located at the second level (LEV2). The second level LEV2 may be higher than the first level LEV1.

The contacts CNT contacting the lower interconnections LML of the first peripheral circuit region PER1 may be arranged in a zigzag shape in the second direction D2 . Since the contacts CNTs on the first peripheral circuit region PER1 are arranged in a zigzag shape, a process margin between adjacent contacts CNTs may be sufficiently secured. For example, the first lower line LML of the first peripheral circuit area PER1 may have a first end EN1. The second lower wire LML of the first peripheral circuit area PER1 may have a second end EN2. The second end EN2 may be closer to the contact region CTR than the first end EN1 .

Third and fourth interlayer insulating layers ILD3 and ILD4 may be provided on the second interlayer insulating layer ILD2 . Vias VI may be provided in the third interlayer insulating layers ILD3 . First to sixth interconnections ML1 to ML6 may be provided in the fourth interlayer insulating layers ILD4 . The first to sixth interconnections ML1 to ML6 may contact the vias VI.

On the contact region CTR, the first to fourth wires ML1 to ML4 are connected to the first conductive lines of the first to fourth stacked structures SS1 to SS4 through the contacts CNT and the vias VI. It may be electrically connected to the (CL1).

On the contact region CTR, the first wires ML1 may be connected to the first conductive lines CL1 of the first stacked structure SS1 , respectively. On the contact region CTR, the second interconnections ML2 may be connected to the first conductive lines CL1 of the second stacked structure SS2, respectively. On the contact region CTR, the third interconnections ML3 may be connected to the first conductive lines CL1 of the third stacked structure SS3, respectively. On the contact region CTR, the fourth interconnections ML4 may be connected to the first conductive lines CL1 of the fourth stacked structure SS4 , respectively.

The number of first wires ML1 may be the same as the number of first conductive lines CL1 of the first stacked structure SS1 . The number of second wires ML2 may be the same as the number of first conductive lines CL1 of the second stacked structure SS2 . The number of third wires ML3 may be the same as the number of first conductive lines CL1 of the third stacked structure SS3 . The number of fourth wires ML4 may be the same as the number of first conductive lines CL1 of the fourth stacked structure SS4 .

Each of the first to fourth wires ML1 - ML4 may include a first portion extending in the first direction D1 and a second portion extending in the second direction D2 . For example, the first portions of the first wires ML1 may be spaced apart from each other by a predetermined interval in the second direction D2. Second portions of the first interconnections ML1 may be connected to the contacts CNT on the first conductive lines CL1.

The first to fourth interconnections ML1 to ML4 may extend from the contact region CTR to the first peripheral circuit region PER1. On the first peripheral circuit area PER1 , the first to fourth wires ML1 to ML4 may be electrically connected to the lower wires LML through the contacts CNT and the vias VI.

On the cell area CAR, the fifth wires ML5 may be electrically connected to the second conductive lines CL2 through the vias VI. The fifth wires ML5 may extend in the second direction D2. The fifth interconnections ML5 may extend from the cell area CAR to the second peripheral circuit areas PER2. On the second peripheral circuit regions PER2 , the fifth interconnections ML5 may be electrically connected to the lower interconnections LML through the contacts CNT and vias VI.

Each of the fifth interconnections ML5 may be connected in common with the second conductive lines CL2 of the first to fourth stacked structures SS1 to SS4 . For example, the second conductive lines CL2 arranged in the first direction D1 of the second stacked structure SS2 may form a first row C1. The second conductive lines CL2 arranged in the first direction D1 of the third stacked structure SS3 may form a second row C2.

The first second conductive line CL2 of the first row C1 and the first second conductive line CL2 of the second row C2 may be aligned in the second direction D2. The first second conductive line CL2 of the first row C1 and the first second conductive line CL2 of the second row C2 may be connected to the first fifth wire ML5 in common. The second second conductive line CL2 of the first row C1 and the second second conductive line CL2 of the second row C2 may be aligned in the second direction D2. The second second conductive line CL2 of the first row C1 and the second second conductive line CL2 of the second row C2 may be connected to the second fifth wire ML5 in common.

The first fifth interconnection ML5 may extend onto the second peripheral circuit area PER2 adjacent to one side of the cell area CAR. The second fifth wire ML5 may extend onto the second peripheral circuit area PER2 adjacent to the other side of the cell area CAR.

On the cell region CAR, the sixth interconnection ML6 may be electrically connected to the third conductive lines CL3 through the vias VI. The sixth wire ML6 may extend in the second direction D2. The sixth wire ML6 may be connected to an upper wire (not shown) through the upper via UVI.

Each of the lower interconnection LML, lower contact LCNT, contacts CNT, vias VI, and first to sixth interconnections ML1 to ML6 is made of aluminum, copper, tungsten, molybdenum, and cobalt. It may include at least one selected metal material.

Hereinafter, various embodiments of the present invention will be described. In the embodiments to be described later, detailed descriptions of technical features overlapping those previously described with reference to FIGS. 1 to 6B will be omitted, and differences will be described in detail.

7A is a cross-sectional view taken along lines A-A' and B-B' of FIG. 5; FIG. 7B is a cross-sectional view taken along line C-C′ of FIG. 5 . Referring to FIGS. 7A and 7B , first peripheral transistors PTR1 may be disposed on the first and second peripheral circuit regions PER1 and PER2 . Furthermore, at least one second peripheral transistor PTR2 may be disposed on the contact region CTR, and at least one third peripheral transistor PTR3 may be disposed on the cell region CAR.

The second and third peripheral transistors PTR2 and PTR3 may be transistors that perform the same function as the first peripheral transistors PTR1 of the first and second peripheral circuit regions PER1 and PER2 . For example, the second and third peripheral transistors PTR2 and PTR3 together with the first peripheral transistors PTR1 may constitute a peripheral circuit for driving a memory cell. According to the present embodiment, the peripheral transistors constituting the peripheral circuit are disposed not only on the first and second peripheral circuit regions PER1 and PER2 but also on the contact region CTR and cell region CAR, so that the peripheral transistors are formed. A relatively large area can be secured.

First lower interconnections LML1 may be provided on the device isolation layer ST of the substrate 100 . The first lower interconnections LML1 may be disposed on the contact area CTR and the cell area CAR.

A first interlayer insulating layer ILD1 may cover the first to third peripheral transistors PTR1 , PTR2 , and PTR3 and the first lower wires LML1 . An additional interlayer insulating layer ILDa may be provided between the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2. Second lower interconnections LML2 may be provided in the additional interlayer insulating layer ILDa.

For example, the second lower wire LML2 may be connected to the second peripheral transistor PTR2 through the lower contact LCNT penetrating the first interlayer insulating layer ILD1. As a result, the first conductive line CL1 may be electrically connected to the second peripheral transistor PTR2.

The first and second lower interconnections LML1 and LML2 are disposed on the contact region CTR and the cell region CAR as well as the first and second peripheral circuit regions PER1 and PER2 to perform routing of the memory device. degree of freedom can be improved. Furthermore, it is possible to secure a relatively large area in which wires are formed.

8A is a cross-sectional view taken along lines A-A' and B-B' of FIG. 5; FIG. 8B is a cross-sectional view taken along line C-C′ of FIG. 5 . Referring to FIGS. 8A and 8B , a fifth interlayer insulating layer ILD5 and a sixth interlayer insulating layer ILD6 may be provided on the fourth interlayer insulating layer ILD4 . Upper vias UVI may be provided in the fifth interlayer insulating layers ILD5. Upper interconnections UML may be provided in the sixth interlayer insulating layers ILD6. Upper interconnections UML may contact upper vias UVI. The upper vias UVI may vertically connect the upper wires UML and the first to sixth wires ML1 to ML6 to each other.

Referring to FIG. 8A , the first and fourth wires ML4 may be electrically connected to the upper wires UML. The upper wiring UML connected to the first fourth wiring ML4 may extend to the first peripheral circuit area PER1. The second fourth wire ML4 may extend into the first peripheral circuit region PER1 without being connected to the upper wire UML. The third and fourth wire ML4 may be electrically connected to the upper wire UML. An upper interconnection UML connected to the third and fourth interconnection ML4 may extend to the first peripheral circuit region PER1. The fourth wire ML4 may extend into the first peripheral circuit region PER1 without being connected to the upper wire UML.

Referring to FIG. 8B , the first fifth wire ML5 may be electrically connected to the upper wire UML. The upper wiring UML connected to the first fifth wiring ML5 may extend to the second peripheral circuit area PER2. The second fifth wire ML5 may extend to the second peripheral circuit area PER2 without being connected to the upper wire UML.

According to the present embodiment, upper wirings UML, which are upper wirings, are additionally disposed on the first to sixth wirings ML1 - ML6 to improve routing freedom. Furthermore, it is possible to secure a relatively large area in which wires are formed.

9 is a cross-sectional view taken along line C-C′ of FIG. 5; Referring to FIGS. 7A and 9 , a second conductive line CL2 and an additional conductive line ( CL2a) may be provided. In other words, the second conductive line CL2 and the additional conductive line CL2a may be disposed on both sides of the vertically stacked semiconductor patterns SP. The additional conductive line CL2a may extend parallel to the second conductive line CL2 in the third direction D3.

For example, the additional conductive line CL2a may be a back gate of the memory cell transistor MCT. As another example, the additional conductive line CL2a and the second conductive line CL2 may constitute one word line WL. As another example, the additional conductive line CL2a may directly contact the semiconductor patterns SP and perform a body contact function. The additional conductive line CL2a may be connected to other regions through the first and second lower interconnections LML1 and LML2.

10 is a cross-sectional view along lines A-A' and B-B' of FIG. 5; Referring to FIG. 10 , a semiconductor layer SL may be provided on the second interlayer insulating layer ILD2 of the first peripheral circuit region PER1. The semiconductor layer SL may be positioned higher than the first to fourth stacked structures SS1 - SS4 . Peripheral transistors PTR may be formed on the semiconductor layer SL. Structures of peripheral transistors on the second peripheral circuit regions PER2 may be substantially the same as structures of peripheral transistors on the first peripheral circuit region PER1 shown in FIG. 10 .

An additional interlayer insulating layer ILDa may be provided on the semiconductor layer SL to cover the peripheral transistors PTR. A top surface of the additional interlayer insulating film ILDa may be substantially coplanar with a top surface of the second interlayer insulating film ILD2 on the contact region CTR and the cell region CAR. The peripheral transistors PTR on the semiconductor layer SL may be electrically connected to the first and second conductive lines CL1 and CL2 through the first to fifth wires ML1 to ML5.

11 is a perspective view illustrating a 3D semiconductor memory device according to example embodiments. FIG. 12 is a cross-sectional view taken along line A-A' of FIG. 5 . Referring to FIGS. 11 and 12 , the first peripheral circuit area PER1 may include a first sub area PER1a and a second sub area PER1b. The second subregion PER1b may be spaced apart from the first subregion PER1a in the first direction D1. First and second peripheral transistors PTR1 and PTR2 may be provided on the first and second subregions PER1a and PER1b, respectively.

For example, the first fourth line ML4 may extend into the first sub-region PER1a. The second fourth line ML4 may extend to the second subregion PER1b. The third and fourth wire ML4 may extend to the first sub-region PER1a. The fourth line ML4 may extend to the second subregion PER1b.

According to this embodiment, the first and second sub-regions PER1a and PER1b may be formed by dividing the first peripheral circuit region PER1 into two regions. Accordingly, the first and second peripheral transistors PTR1 and PTR2 constituting the peripheral circuit of the first peripheral circuit region PER1 may be divided into first and second sub regions PER1a and PER1b and disposed. . As a result, a relatively large area for forming peripheral transistors can be secured, and a relatively large distance between adjacent contacts CNTs can be secured.

13 is a perspective view illustrating a 3D semiconductor memory device according to example embodiments. Referring to FIG. 13 , a plurality of first peripheral circuit regions PER1 may be provided. For example, the first peripheral circuit regions PER1 may include sense amplifiers.

Adjacent to one side of the cell area CAR, first peripheral circuit areas PER1 and second peripheral circuit areas PER2 may be alternately arranged along the first direction D1 . Adjacent to the other side of the cell area CAR, first peripheral circuit areas PER1 and second peripheral circuit areas PER2 may be alternately arranged along the first direction D1 .

14 is a perspective view illustrating a 3D semiconductor memory device according to example embodiments. Referring to FIG. 14 , the first peripheral circuit area PER1 includes a first portion PA1 extending in the second direction D2 and a second portion extending from the first portion PA1 in the first direction D1. s (PA2) may be included.

According to the embodiments described with reference to FIGS. 13 and 14 , a larger area of the first peripheral circuit region PER1 can be secured compared to the area of the first peripheral circuit region PER1 previously described with reference to FIG. 5 . there is.

15 is a perspective view illustrating a 3D semiconductor memory device according to example embodiments. 16 is a cross-sectional view taken along the line A-A' of FIG. 15; Referring to FIGS. 15 and 16 , common contacts CCNT contacting the first conductive lines CL1 may be provided on the contact region CTR. Each of the common contacts CCNT may come into common contact with a pair of first conductive lines CL1 positioned at the same level as each other.

For example, the lowermost first conductive line CL1 of the second stacked structure SS2 and the lowermost first conductive line CL1 of the third stacked structure SS3 share one common contact CCNT. can be connected to The uppermost first conductive line CL1 of the second stacked structure SS2 and the uppermost first conductive line CL1 of the third stacked structure SS3 may be connected in common to one common contact CCNT. .

Common wires CML may be provided instead of the first to fourth wires ML1 to ML4 of FIG. 5 . Common wires CML may be electrically connected to common contacts CCNT through vias VI. Each of the common wires CML may be electrically connected to a pair of first conductive lines CL1 positioned at the same level as each other.

Although not shown, in another exemplary embodiment of the present invention, the common contact CCNT includes the first conductive line CL1 of the first stack structure SS1 and the first conductive line CL1 of the second stack structure SS2. It may be provided to contact in common with. The common contact CCNT may be provided to contact the first conductive line CL1 of the third stacked structure SS3 and the first conductive line CL1 of the fourth stacked structure SS4 in common.

The fifth wires ML5 may include first sub-wires ML5a and second sub-wires ML5b. The first sub-wires ML5a and the second sub-wires ML5b may be alternately arranged along the first direction D1. Each of the first sub-wires ML5a may be connected to the second conductive lines CL2 of the second and fourth stacked structures SS2 and SS4 in common. Each of the first sub-wires ML5a may not be connected to the second conductive lines CL2 of the first and third stacked structures SS1 and SS3. Each of the second sub-wires ML5b may be connected to the second conductive lines CL2 of the first and third stacked structures SS1 and SS3 in common. Each of the second sub-wires ML5b may not be connected to the second conductive lines CL2 of the second and fourth stacked structures SS2 and SS4 .

For example, the second conductive lines CL2 of the second stacked structure SS2 may form the first row C1, and the second conductive lines CL2 of the third stacked structure SS3 may form the second row C1. Row C2 can be achieved. The first second conductive line CL2 of the first row C1 and the first second conductive line CL2 of the second row C2 may not be aligned in the second direction D2 and may be offset from each other. The first second conductive line CL2 of the first row C1 may be electrically connected to the first sub-wire ML5a, and the first second conductive line CL2 of the second row C2 may be electrically connected to the second sub-wire ML5a. It may be electrically connected to the sub wire ML5b. The second second conductive line CL2 of the first row C1 and the second second conductive line CL2 of the second row C2 may not be aligned in the second direction D2 and may be offset from each other. The second conductive line CL2 of the first row C1 may be electrically connected to the first sub-wire ML5a, and the second second conductive line CL2 of the second row C2 may be electrically connected to the second sub-wire ML5a. It may be electrically connected to the sub wire ML5b.

The first sub-wires ML5a may extend from the cell area CAR onto the second peripheral circuit area PER2 adjacent to one side of the cell area CAR. The second sub wires ML5b may extend from the cell area CAR onto the second peripheral circuit area PER2 adjacent to the other side of the cell area CAR.

The contacts CNT contacting the lower interconnections LML of the second peripheral circuit region PER2 may be arranged in a zigzag shape in the second direction D2 . Since the contacts CNT on the second peripheral circuit region PER2 are arranged in a zigzag shape, a process margin between adjacent contacts CNT may be sufficiently secured. For example, the first lower wire LML of the second peripheral circuit area PER2 may have a first end EN1. The second lower wire LML of the second peripheral circuit area PER2 may have a second end EN2. The second end EN2 may be closer to the contact region CTR than the first end EN1 .

17 is a perspective view illustrating a 3D semiconductor memory device according to example embodiments. 18 is a cross-sectional view along lines A-A' and B-B' of FIG. 17; 17 and 18, each of the first conductive lines CL1 includes a wiring part LP extending in the first direction D1 and a contact part extending from the wiring part LP in the third direction D3. (CNP).

The contact portions CNP of the first conductive lines CL1 may be disposed on the contact region CTR. The contact portions CNP of each of the first to fourth stacked structures SS1 to SS4 may be arranged in the first direction D1. Top surfaces of the contact portions CNP may be substantially coplanar with a top surface of the second interlayer insulating layer ILD2 . Vias VI may be disposed on upper surfaces of the contact portions CNP. The contact portions CNP may be electrically connected to the first to fourth wires ML1 to ML4 through the vias VI.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, the present invention may be embodied in other specific forms without changing its technical spirit or essential features. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

Claims (20)

a first laminated structure and a second laminated structure on a substrate; and
Including a first wiring, a second wiring, and a third wiring on the first and second laminated structures,
Each of the first and second laminated structures:
vertically stacked semiconductor patterns;
conductive lines connected to the semiconductor patterns and extending horizontally; and
A gate electrode extending vertically adjacent to the semiconductor patterns;
The conductive lines of the first laminated structure include a first conductive line,
The conductive lines of the second laminated structure include a second conductive line positioned at the same level as the first conductive line,
The first wiring is connected in common with the first and second conductive lines,
The second wiring is electrically connected to the gate electrode of the first stacked structure,
The third wiring is electrically connected to the gate electrode of the second stacked structure.
delete delete delete According to claim 1,
Further comprising a common contact contacting the first and second conductive lines in common;
The first wiring is electrically connected to the common contact.
According to claim 1,
Each of the semiconductor patterns includes a first impurity region, a second impurity region, and a channel region interposed between the first and second impurity regions;
Each of the conductive lines is electrically connected to the first impurity region of each of the semiconductor patterns,
Each of the gate electrodes is adjacent to the channel regions of the semiconductor patterns.
According to claim 6,
Each of the semiconductor patterns further includes an end film interposed between the first impurity region and the conductive line;
The semiconductor memory device of claim 1 , wherein the end film includes a semiconductor element having a narrower band gap than a semiconductor element of the channel region.
According to claim 1,
The first and second laminated structures extend in a first direction parallel to each other,
The conductive lines of each of the first and second stacked structures extend in the first direction,
The semiconductor memory device of claim 1 , wherein the semiconductor patterns of each of the first and second stacked structures extend in a second direction crossing the first direction.
According to claim 1,
the substrate includes a first peripheral circuit area and a second peripheral circuit area;
the first wire extends toward the first peripheral circuit region in a first direction and is electrically connected to a first peripheral transistor on the first peripheral circuit region;
The second wire extends toward the second peripheral circuit area in a second direction crossing the first direction, and is electrically connected to a second peripheral transistor on the second peripheral circuit area.
According to claim 1,
Further comprising a contact contacting the first and second conductive lines in common;
The substrate includes a cell region and a contact region,
The conductive lines of the first and second stacked structures extend from the cell region to the contact region;
the contact is disposed on the contact area;
The first wire is a semiconductor memory device electrically connected to the contact.
According to claim 1,
The substrate includes a cell region and a contact region,
Each of the conductive lines of the first and second stacked structures:
a wiring part extending horizontally from the cell region to the contact region; and
A contact portion extending vertically from the wiring portion on the contact area;
The first wire is commonly connected to the contact portions of the first and second conductive lines.
a substrate including a cell region and a contact region;
semiconductor patterns stacked vertically on the cell region, each of the semiconductor patterns including a first impurity region, a second impurity region, and a channel region between the first and second impurity regions;
first conductive lines connected to the first impurity regions of the semiconductor patterns, the first conductive lines extending horizontally from the cell region to the contact region;
capacitors connected to the second impurity regions of the semiconductor patterns; and
Including contacts contacting the first conductive lines on the contact area,
The contacts include a first contact and a second contact closer to the cell region than the first contact;
The semiconductor memory device of claim 1 , wherein a level of a bottom surface of the second contact is higher than a level of a bottom surface of the first contact.
According to claim 12,
The first conductive line contacting the first contact has a first length in the contact region;
The first conductive line contacting the second contact has a second length on the contact area;
The first length is greater than the second length semiconductor memory device.
According to claim 12,
a first wire and a second wire electrically connected to the first and second contacts, respectively;
Further comprising a first lower wiring and a second lower wiring on the peripheral circuit area of the substrate,
The first and second lower wires are electrically connected to the first and second wires, respectively;
The first and second lower wires each include a first end and a second end,
The second end is closer to the contact region than the first end.
According to claim 12,
a second conductive line extending vertically adjacent to the channel regions of the semiconductor patterns;
a first wire electrically connected to the first contact; and
Further comprising a second wire electrically connected to the second conductive line,
the substrate further includes first and second peripheral circuit regions;
The first and second wires extend over the first and second peripheral circuit regions, respectively.
According to claim 12,
The semiconductor patterns extend in a first direction,
The first conductive lines extend in a second direction crossing the first direction.
a first laminated structure and a second laminated structure on a substrate; and
Including a first wiring, a second wiring, and a third wiring on the first and second laminated structures,
The substrate includes a cell region, a contact region, a first peripheral circuit region, and a second peripheral circuit region;
The first wire extends in a first direction, the second wire extends in a second direction crossing the first direction,
Each of the first and second laminated structures:
memory cell transistors three-dimensionally arranged;
a bit line connected to the horizontally arranged memory cell transistors; and
a word line connected to the vertically arranged memory cell transistors;
On the contact region, the first wiring is connected in common with the bit lines of the first and second stacked structures,
On the cell region, the second wiring is electrically connected to the word line of the first stacked structure;
On the cell region, the third wire is electrically connected to the word line of the second stacked structure.
According to claim 17,
the bit line extends parallel to the upper surface of the substrate;
The word line extends perpendicularly to the upper surface of the substrate.
According to claim 17,
The semiconductor memory device of claim 1 , wherein the bit line of the first stack structure and the bit line of the second stack structure are located at substantially the same level as each other.
According to claim 17,
The first wire extends from the contact area to the first peripheral circuit area;
The second and third wires extend from the cell region to the second peripheral circuit region.

Images