SG10201503789YA - Method For Etching Etching Target Layer - Google Patents

Method For Etching Etching Target Layer

Info

Publication number
SG10201503789YA
SG10201503789YA SG10201503789YA SG10201503789YA SG10201503789YA SG 10201503789Y A SG10201503789Y A SG 10201503789YA SG 10201503789Y A SG10201503789Y A SG 10201503789YA SG 10201503789Y A SG10201503789Y A SG 10201503789YA SG 10201503789Y A SG10201503789Y A SG 10201503789YA
Authority
SG
Singapore
Prior art keywords
etching
target layer
etching target
layer
etching etching
Prior art date
Application number
SG10201503789YA
Inventor
Shin Hirotsu
Yoshiki Igarashi
Tomonori Miwa
Hiroshi Okada
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of SG10201503789YA publication Critical patent/SG10201503789YA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082—Radio frequency generated discharge
    • H01J37/32091—Radio frequency generated discharge the radio frequency energy being capacitively coupled to the plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082—Radio frequency generated discharge
    • H01J37/32137—Radio frequency generated discharge controlling of the discharge by modulation of energy
    • H01J37/32155—Frequency modulation
    • H01J37/32165—Plural frequencies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
SG10201503789YA 2014-05-14 2015-05-13 Method For Etching Etching Target Layer SG10201503789YA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2014100538A JP6289996B2 (en) 2014-05-14 2014-05-14 Method for etching a layer to be etched

Publications (1)

Publication Number Publication Date
SG10201503789YA true SG10201503789YA (en) 2015-12-30

Family

ID=54539115

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10201503789YA SG10201503789YA (en) 2014-05-14 2015-05-13 Method For Etching Etching Target Layer

Country Status (5)

Country Link
US (1) US9418863B2 (en)
JP (1) JP6289996B2 (en)
KR (1) KR101863992B1 (en)
CN (1) CN105097498B (en)
SG (1) SG10201503789YA (en)

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* Cited by examiner, † Cited by third party
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JP6604833B2 (en) * 2015-12-03 2019-11-13 東京エレクトロン株式会社 Plasma etching method
US9997374B2 (en) * 2015-12-18 2018-06-12 Tokyo Electron Limited Etching method
KR102356741B1 (en) 2017-05-31 2022-01-28 삼성전자주식회사 Semiconductor device including insulating layers and method of forming the same
TWI812762B (en) * 2018-07-30 2023-08-21 日商東京威力科創股份有限公司 Method, device and system for processing object
US11532484B2 (en) * 2018-10-26 2022-12-20 Hitachi High-Tech Corporation Plasma processing apparatus and plasma processing method
CN115380365A (en) * 2020-02-13 2022-11-22 朗姆研究公司 High aspect ratio etch with infinite selectivity
WO2023215040A1 (en) * 2022-05-02 2023-11-09 Lam Research Corporation Co-deposition and etch process

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KR100230981B1 (en) * 1996-05-08 1999-11-15 김광호 Plasma etching method for manufacturing process of semiconductor device
US5942446A (en) * 1997-09-12 1999-08-24 Taiwan Semiconductor Manufacturing Company, Ltd. Fluorocarbon polymer layer deposition predominant pre-etch plasma etch method for forming patterned silicon containing dielectric layer
KR100881472B1 (en) * 1999-02-04 2009-02-05 어플라이드 머티어리얼스, 인코포레이티드 A method for depositing built-up structures upon a patterned mask surface resting on a predetermined substrate
US6372634B1 (en) * 1999-06-15 2002-04-16 Cypress Semiconductor Corp. Plasma etch chemistry and method of improving etch control
JP3927768B2 (en) * 2000-11-17 2007-06-13 松下電器産業株式会社 Manufacturing method of semiconductor device
WO2002086957A1 (en) * 2001-04-19 2002-10-31 Tokyo Electron Limited Dry etching method
EP1387395B1 (en) * 2002-07-31 2016-11-23 Micron Technology, Inc. Method for manufacturing semiconductor integrated circuit structures
US7250371B2 (en) * 2003-08-26 2007-07-31 Lam Research Corporation Reduction of feature critical dimensions
US6911399B2 (en) * 2003-09-19 2005-06-28 Applied Materials, Inc. Method of controlling critical dimension microloading of photoresist trimming process by selective sidewall polymer deposition
JP4727171B2 (en) * 2003-09-29 2011-07-20 東京エレクトロン株式会社 Etching method
JP4550507B2 (en) * 2004-07-26 2010-09-22 株式会社日立ハイテクノロジーズ Plasma processing equipment
JP2007294905A (en) * 2006-03-30 2007-11-08 Hitachi High-Technologies Corp Method of manufacturing semiconductor and etching system
US7541292B2 (en) * 2006-04-28 2009-06-02 Applied Materials, Inc. Plasma etch process with separately fed carbon-lean and carbon-rich polymerizing etch gases in independent inner and outer gas injection zones
US8231799B2 (en) * 2006-04-28 2012-07-31 Applied Materials, Inc. Plasma reactor apparatus with multiple gas injection zones having time-changing separate configurable gas compositions for each zone
JP4551913B2 (en) * 2007-06-01 2010-09-29 株式会社東芝 Manufacturing method of semiconductor device
US7629255B2 (en) * 2007-06-04 2009-12-08 Lam Research Corporation Method for reducing microloading in etching high aspect ratio structures
US7838426B2 (en) * 2007-08-20 2010-11-23 Lam Research Corporation Mask trimming
JP5192214B2 (en) * 2007-11-02 2013-05-08 東京エレクトロン株式会社 Gas supply apparatus, substrate processing apparatus, and substrate processing method
US20090156011A1 (en) * 2007-12-12 2009-06-18 Belen Rodolfo P Method of controlling CD bias and CD microloading by changing the ceiling-to-wafer gap in a plasma reactor
CN101625966A (en) * 2008-07-11 2010-01-13 东京毅力科创株式会社 Substrate processing method
US9122832B2 (en) * 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
US8097911B2 (en) * 2008-12-31 2012-01-17 Intel Corporation Etch stop structures for floating gate devices
US8809196B2 (en) * 2009-01-14 2014-08-19 Tokyo Electron Limited Method of etching a thin film using pressure modulation
US8658541B2 (en) * 2010-01-15 2014-02-25 Applied Materials, Inc. Method of controlling trench microloading using plasma pulsing
US8574447B2 (en) * 2010-03-31 2013-11-05 Lam Research Corporation Inorganic rapid alternating process for silicon etch
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JP5932599B2 (en) * 2011-10-31 2016-06-08 株式会社日立ハイテクノロジーズ Plasma etching method
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Also Published As

Publication number Publication date
JP2015220251A (en) 2015-12-07
JP6289996B2 (en) 2018-03-07
US20150332932A1 (en) 2015-11-19
US9418863B2 (en) 2016-08-16
KR20150130920A (en) 2015-11-24
CN105097498B (en) 2018-11-20
CN105097498A (en) 2015-11-25
KR101863992B1 (en) 2018-06-01

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