SG10201501810WA - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
SG10201501810WA
SG10201501810WA SG10201501810WA SG10201501810WA SG10201501810WA SG 10201501810W A SG10201501810W A SG 10201501810WA SG 10201501810W A SG10201501810W A SG 10201501810WA SG 10201501810W A SG10201501810W A SG 10201501810WA SG 10201501810W A SG10201501810W A SG 10201501810WA
Authority
SG
Singapore
Prior art keywords
semiconductor device
semiconductor
Prior art date
Application number
SG10201501810WA
Other languages
English (en)
Inventor
Fukuda Shohei
Original Assignee
Toshiba Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Kk filed Critical Toshiba Kk
Publication of SG10201501810WA publication Critical patent/SG10201501810WA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H01L27/0285—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements bias arrangements for gate electrode of field effect transistors, e.g. RC networks, voltage partitioning circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
SG10201501810WA 2014-09-24 2015-03-10 Semiconductor device SG10201501810WA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2014193831A JP2016066673A (ja) 2014-09-24 2014-09-24 半導体装置

Publications (1)

Publication Number Publication Date
SG10201501810WA true SG10201501810WA (en) 2016-04-28

Family

ID=52813892

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10201501810WA SG10201501810WA (en) 2014-09-24 2015-03-10 Semiconductor device

Country Status (6)

Country Link
US (1) US20160086935A1 (zh)
EP (1) EP3001455A1 (zh)
JP (1) JP2016066673A (zh)
KR (1) KR20160035959A (zh)
SG (1) SG10201501810WA (zh)
TW (1) TWI574371B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230327428A1 (en) * 2022-04-12 2023-10-12 Mediatek Inc. Distributed electro-static discharge protection
TWI828550B (zh) * 2023-03-01 2024-01-01 智原科技股份有限公司 佈線方法、電腦程式產品及與其相關之積體電路

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5825601A (en) * 1997-06-16 1998-10-20 Lsi Logic Corporation Power supply ESD protection circuit
JP4132270B2 (ja) * 1998-04-20 2008-08-13 三菱電機株式会社 半導体集積回路装置
US7446990B2 (en) * 2005-02-11 2008-11-04 Freescale Semiconductor, Inc. I/O cell ESD system
WO2013051175A1 (ja) * 2011-10-06 2013-04-11 パナソニック株式会社 半導体集積回路装置
CN103795049B (zh) * 2012-10-29 2017-03-01 台湾积体电路制造股份有限公司 使用i/o焊盘的esd保护电路

Also Published As

Publication number Publication date
TW201613062A (en) 2016-04-01
KR20160035959A (ko) 2016-04-01
JP2016066673A (ja) 2016-04-28
EP3001455A1 (en) 2016-03-30
TWI574371B (zh) 2017-03-11
US20160086935A1 (en) 2016-03-24

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