SE9803370D0 - Metod och arrangemang för minneshantering - Google Patents
Metod och arrangemang för minneshanteringInfo
- Publication number
- SE9803370D0 SE9803370D0 SE9803370A SE9803370A SE9803370D0 SE 9803370 D0 SE9803370 D0 SE 9803370D0 SE 9803370 A SE9803370 A SE 9803370A SE 9803370 A SE9803370 A SE 9803370A SE 9803370 D0 SE9803370 D0 SE 9803370D0
- Authority
- SE
- Sweden
- Prior art keywords
- memory
- time slots
- arrangement
- management
- memory management
- Prior art date
Links
- 230000015654 memory Effects 0.000 title abstract 9
- 230000002596 correlated effect Effects 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1658—Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1647—Handling requests for interconnection or transfer for access to memory bus based on arbitration with interleaved bank access
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1666—Error detection or correction of the data by redundancy in hardware where the redundant component is memory or memory area
- G06F11/167—Error detection by comparing the memory output
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
- G06F11/2038—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant with a single idle spare processing component
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
- G06F11/2043—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant where the redundant components share a common memory address space
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Multi Processors (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SE9803370A SE515461C2 (sv) | 1998-10-05 | 1998-10-05 | Metod och arrangemang för minneshantering |
EP99970185A EP1208441A2 (en) | 1998-10-05 | 1999-10-04 | Method and arrangement for memory management |
AU11953/00A AU1195300A (en) | 1998-10-05 | 1999-10-04 | Method and arrangement for memory management |
PCT/SE1999/001760 WO2000020973A2 (en) | 1998-10-05 | 1999-10-04 | Method and arrangement for memory management |
US09/412,635 US6425063B1 (en) | 1998-10-05 | 1999-10-05 | Method and arrangement for memory management |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SE9803370A SE515461C2 (sv) | 1998-10-05 | 1998-10-05 | Metod och arrangemang för minneshantering |
Publications (3)
Publication Number | Publication Date |
---|---|
SE9803370D0 true SE9803370D0 (sv) | 1998-10-05 |
SE9803370L SE9803370L (sv) | 2000-04-06 |
SE515461C2 SE515461C2 (sv) | 2001-08-06 |
Family
ID=20412821
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SE9803370A SE515461C2 (sv) | 1998-10-05 | 1998-10-05 | Metod och arrangemang för minneshantering |
Country Status (5)
Country | Link |
---|---|
US (1) | US6425063B1 (sv) |
EP (1) | EP1208441A2 (sv) |
AU (1) | AU1195300A (sv) |
SE (1) | SE515461C2 (sv) |
WO (1) | WO2000020973A2 (sv) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8255435B2 (en) * | 2004-10-07 | 2012-08-28 | International Business Machines Corporation | Detecting memory management anti-patterns |
US7733854B2 (en) * | 2004-11-30 | 2010-06-08 | Broadcom Corporation | Forced bubble insertion scheme |
DE102006019426B4 (de) * | 2006-04-26 | 2008-03-13 | Qimonda Ag | Speichermodulsteuerung, Speichersteuerung und entsprechende Speicheranordnung sowie Verfahren zur Fehlerkorrektur |
KR101131376B1 (ko) * | 2008-03-31 | 2012-04-04 | 인텔 코오퍼레이션 | 파션-프리 멀티-소켓 메모리 시스템 아키텍쳐 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3970993A (en) * | 1974-01-02 | 1976-07-20 | Hughes Aircraft Company | Cooperative-word linear array parallel processor |
US5155807A (en) * | 1986-02-24 | 1992-10-13 | International Business Machines Corporation | Multi-processor communications channel utilizing random access/sequential access memories |
CA1293819C (en) * | 1986-08-29 | 1991-12-31 | Thinking Machines Corporation | Very large scale computer |
US4965717A (en) * | 1988-12-09 | 1990-10-23 | Tandem Computers Incorporated | Multiple processor system having shared memory with private-write capability |
JP2584113B2 (ja) * | 1989-07-21 | 1997-02-19 | 松下電器産業株式会社 | データ転送方法及びデータ転送装置 |
US5283886A (en) * | 1989-08-11 | 1994-02-01 | Hitachi, Ltd. | Multiprocessor cache system having three states for generating invalidating signals upon write accesses |
US5175847A (en) * | 1990-09-20 | 1992-12-29 | Logicon Incorporated | Computer system capable of program execution recovery |
US5313625A (en) * | 1991-07-30 | 1994-05-17 | Honeywell Inc. | Fault recoverable computer system |
JP2974526B2 (ja) * | 1992-12-18 | 1999-11-10 | 富士通株式会社 | データ転送処理方法及びデータ転送処理装置 |
DE69608124T2 (de) * | 1995-12-18 | 2001-04-26 | Abb Automation Inc., Wickliffe | Prozessorunabhängige fehlerprüfungsanordnung |
JP3269967B2 (ja) * | 1996-04-24 | 2002-04-02 | 株式会社日立製作所 | キャッシュコヒーレンシ制御方法、および、これを用いたマルチプロセッサシステム |
US6134673A (en) * | 1997-05-13 | 2000-10-17 | Micron Electronics, Inc. | Method for clustering software applications |
US6061750A (en) * | 1998-02-20 | 2000-05-09 | International Business Machines Corporation | Failover system for a DASD storage controller reconfiguring a first processor, a bridge, a second host adaptor, and a second device adaptor upon a second processor failure |
-
1998
- 1998-10-05 SE SE9803370A patent/SE515461C2/sv not_active IP Right Cessation
-
1999
- 1999-10-04 EP EP99970185A patent/EP1208441A2/en not_active Withdrawn
- 1999-10-04 WO PCT/SE1999/001760 patent/WO2000020973A2/en not_active Application Discontinuation
- 1999-10-04 AU AU11953/00A patent/AU1195300A/en not_active Abandoned
- 1999-10-05 US US09/412,635 patent/US6425063B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US6425063B1 (en) | 2002-07-23 |
SE515461C2 (sv) | 2001-08-06 |
AU1195300A (en) | 2000-04-26 |
EP1208441A2 (en) | 2002-05-29 |
SE9803370L (sv) | 2000-04-06 |
WO2000020973A3 (en) | 2000-07-20 |
WO2000020973A2 (en) | 2000-04-13 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
NUG | Patent has lapsed |