DE69604297D1 - Segmentierte leseleitungsschaltung insbesondere für multiport speicheranordnungen - Google Patents
Segmentierte leseleitungsschaltung insbesondere für multiport speicheranordnungenInfo
- Publication number
- DE69604297D1 DE69604297D1 DE69604297T DE69604297T DE69604297D1 DE 69604297 D1 DE69604297 D1 DE 69604297D1 DE 69604297 T DE69604297 T DE 69604297T DE 69604297 T DE69604297 T DE 69604297T DE 69604297 D1 DE69604297 D1 DE 69604297D1
- Authority
- DE
- Germany
- Prior art keywords
- line circuit
- reading line
- storage arrangements
- multiport storage
- segmented reading
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/525,431 US5646893A (en) | 1995-09-07 | 1995-09-07 | Segmented read line circuit particularly useful for multi-port storage arrays |
PCT/US1996/011527 WO1997009719A1 (en) | 1995-09-07 | 1996-07-11 | Segmented read line circuit particularly useful for multi-port storage arrays |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69604297D1 true DE69604297D1 (de) | 1999-10-21 |
DE69604297T2 DE69604297T2 (de) | 2000-05-11 |
Family
ID=24093229
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69604297T Expired - Lifetime DE69604297T2 (de) | 1995-09-07 | 1996-07-11 | Segmentierte leseleitungsschaltung insbesondere für multiport speicheranordnungen |
Country Status (4)
Country | Link |
---|---|
US (1) | US5646893A (de) |
EP (1) | EP0848851B1 (de) |
DE (1) | DE69604297T2 (de) |
WO (1) | WO1997009719A1 (de) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5828623A (en) * | 1996-02-23 | 1998-10-27 | Integrated Device Technology, Inc. | Parallel write logic for multi-port memory arrays |
US5831896A (en) * | 1996-12-17 | 1998-11-03 | International Business Machines Corporation | Memory cell |
US6188596B1 (en) | 1999-05-20 | 2001-02-13 | Advanced Micro Devices, Inc. | Layout for semiconductor memory including multi-level sensing |
US6258642B1 (en) * | 1999-05-20 | 2001-07-10 | Advanced Micro Devices, Inc. | Use of functional memory cells as guard cells in a semiconductor memory |
US6278627B1 (en) * | 2000-02-15 | 2001-08-21 | Intel Corporation | Multiple input bit-line detection with phase stealing latch in a memory design |
US6625081B2 (en) * | 2001-08-13 | 2003-09-23 | Micron Technology, Inc. | Synchronous flash memory with virtual segment architecture |
KR100445632B1 (ko) * | 2001-09-26 | 2004-08-25 | 삼성전자주식회사 | 커플링 노이즈를 감소시킬 수 있는 배선 구조 |
US7711337B2 (en) * | 2006-01-14 | 2010-05-04 | Paratek Microwave, Inc. | Adaptive impedance matching module (AIMM) control architectures |
US7626871B1 (en) * | 2007-08-09 | 2009-12-01 | Nvidia Corporation | High-speed single-ended memory read circuit |
US8154936B2 (en) * | 2008-12-30 | 2012-04-10 | Stmicroelectronics Pvt. Ltd. | Single-ended bit line based storage system |
US9489326B1 (en) | 2009-03-09 | 2016-11-08 | Cypress Semiconductor Corporation | Multi-port integrated circuit devices and methods |
US8595398B2 (en) * | 2009-03-09 | 2013-11-26 | Cypress Semiconductor Corp. | Multi-port memory devices and methods |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57152589A (en) * | 1981-03-13 | 1982-09-20 | Fujitsu Ltd | Semiconductor memory |
DE3582828D1 (de) * | 1984-07-26 | 1991-06-20 | Texas Instruments Inc | Dynamischer speicheraufbau mit segmentierten und quasi-gefalteten bitzeilen. |
US5422857A (en) * | 1989-11-21 | 1995-06-06 | Matsushita Electric Industrial Co., Ltd. | Semiconductor memory unit having overlapping addresses |
US5355335A (en) * | 1991-06-25 | 1994-10-11 | Fujitsu Limited | Semiconductor memory device having a plurality of writing and reading ports for decreasing hardware amount |
-
1995
- 1995-09-07 US US08/525,431 patent/US5646893A/en not_active Expired - Lifetime
-
1996
- 1996-07-11 EP EP96923745A patent/EP0848851B1/de not_active Expired - Lifetime
- 1996-07-11 WO PCT/US1996/011527 patent/WO1997009719A1/en active IP Right Grant
- 1996-07-11 DE DE69604297T patent/DE69604297T2/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
WO1997009719A1 (en) | 1997-03-13 |
EP0848851B1 (de) | 1999-09-15 |
EP0848851A1 (de) | 1998-06-24 |
US5646893A (en) | 1997-07-08 |
DE69604297T2 (de) | 2000-05-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |