FR2772970B1 - Procede de test d'une memoire dynamique - Google Patents

Procede de test d'une memoire dynamique

Info

Publication number
FR2772970B1
FR2772970B1 FR9716466A FR9716466A FR2772970B1 FR 2772970 B1 FR2772970 B1 FR 2772970B1 FR 9716466 A FR9716466 A FR 9716466A FR 9716466 A FR9716466 A FR 9716466A FR 2772970 B1 FR2772970 B1 FR 2772970B1
Authority
FR
France
Prior art keywords
testing
retention time
dynamic memory
information
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9716466A
Other languages
English (en)
Other versions
FR2772970A1 (fr
Inventor
Richard Fournel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
SGS Thomson Microelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SA filed Critical SGS Thomson Microelectronics SA
Priority to FR9716466A priority Critical patent/FR2772970B1/fr
Priority to US09/219,470 priority patent/US6097646A/en
Publication of FR2772970A1 publication Critical patent/FR2772970A1/fr
Application granted granted Critical
Publication of FR2772970B1 publication Critical patent/FR2772970B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50016—Marginal testing, e.g. race, voltage or current testing of retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5006—Current

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
FR9716466A 1997-12-24 1997-12-24 Procede de test d'une memoire dynamique Expired - Fee Related FR2772970B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR9716466A FR2772970B1 (fr) 1997-12-24 1997-12-24 Procede de test d'une memoire dynamique
US09/219,470 US6097646A (en) 1997-12-24 1998-12-23 Method for the testing of a dynamic memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9716466A FR2772970B1 (fr) 1997-12-24 1997-12-24 Procede de test d'une memoire dynamique

Publications (2)

Publication Number Publication Date
FR2772970A1 FR2772970A1 (fr) 1999-06-25
FR2772970B1 true FR2772970B1 (fr) 2003-09-26

Family

ID=9515100

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9716466A Expired - Fee Related FR2772970B1 (fr) 1997-12-24 1997-12-24 Procede de test d'une memoire dynamique

Country Status (2)

Country Link
US (1) US6097646A (fr)
FR (1) FR2772970B1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6185125B1 (en) * 1999-12-15 2001-02-06 Winbond Electronics Corp. Circuit for measuring the data retention time of a dynamic random-access memory cell
US7394708B1 (en) * 2005-03-18 2008-07-01 Xilinx, Inc. Adjustable global tap voltage to improve memory cell yield
US8922236B2 (en) * 2010-09-10 2014-12-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor memory device and method for inspecting the same

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5570317A (en) * 1994-07-19 1996-10-29 Intel Corporation Memory circuit with stress circuitry for detecting defects
DE4437967C2 (de) * 1994-10-24 1997-12-04 Lucas Ind Plc Befestigungsring, Vorrichtung für dessen Montage und Montageverfahren für den Befestigungsring
US5568435A (en) * 1995-04-12 1996-10-22 Micron Technology, Inc. Circuit for SRAM test mode isolated bitline modulation
US5689467A (en) * 1995-11-30 1997-11-18 Texas Instruments Incorporated Apparatus and method for reducing test time of the data retention parameter in a dynamic random access memory

Also Published As

Publication number Publication date
US6097646A (en) 2000-08-01
FR2772970A1 (fr) 1999-06-25

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20070831