SE9401814D0 - Bitsynkroniserare - Google Patents

Bitsynkroniserare

Info

Publication number
SE9401814D0
SE9401814D0 SE9401814A SE9401814A SE9401814D0 SE 9401814 D0 SE9401814 D0 SE 9401814D0 SE 9401814 A SE9401814 A SE 9401814A SE 9401814 A SE9401814 A SE 9401814A SE 9401814 D0 SE9401814 D0 SE 9401814D0
Authority
SE
Sweden
Prior art keywords
edge
inverter
pulse
restores
bit stream
Prior art date
Application number
SE9401814A
Other languages
English (en)
Other versions
SE502114C2 (sv
SE9401814L (sv
Inventor
Tord Haulin
Per Segerbaeck
Heinz Maeder
Original Assignee
Ellemtel Utvecklings Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from SE9300679A external-priority patent/SE9300679L/sv
Application filed by Ellemtel Utvecklings Ab filed Critical Ellemtel Utvecklings Ab
Priority to SE9401814A priority Critical patent/SE502114C2/sv
Publication of SE9401814D0 publication Critical patent/SE9401814D0/sv
Publication of SE9401814L publication Critical patent/SE9401814L/sv
Publication of SE502114C2 publication Critical patent/SE502114C2/sv

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Pulse Circuits (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
SE9401814A 1993-03-01 1994-05-26 Bitsynkroniserare SE502114C2 (sv)

Priority Applications (1)

Application Number Priority Date Filing Date Title
SE9401814A SE502114C2 (sv) 1993-03-01 1994-05-26 Bitsynkroniserare

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9300679A SE9300679L (sv) 1993-03-01 1993-03-01 Bitsynkroniserare
SE9401814A SE502114C2 (sv) 1993-03-01 1994-05-26 Bitsynkroniserare

Publications (3)

Publication Number Publication Date
SE9401814D0 true SE9401814D0 (sv) 1994-05-26
SE9401814L SE9401814L (sv) 1994-09-02
SE502114C2 SE502114C2 (sv) 1995-08-21

Family

ID=26661669

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9401814A SE502114C2 (sv) 1993-03-01 1994-05-26 Bitsynkroniserare

Country Status (1)

Country Link
SE (1) SE502114C2 (sv)

Also Published As

Publication number Publication date
SE502114C2 (sv) 1995-08-21
SE9401814L (sv) 1994-09-02

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Legal Events

Date Code Title Description
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