SE9300156D0 - AND ARRANGEMENT FOR A COMPUTER SYSTEM - Google Patents

AND ARRANGEMENT FOR A COMPUTER SYSTEM

Info

Publication number
SE9300156D0
SE9300156D0 SE9300156A SE9300156A SE9300156D0 SE 9300156 D0 SE9300156 D0 SE 9300156D0 SE 9300156 A SE9300156 A SE 9300156A SE 9300156 A SE9300156 A SE 9300156A SE 9300156 D0 SE9300156 D0 SE 9300156D0
Authority
SE
Sweden
Prior art keywords
mode
processor
upgrade
computer system
master
Prior art date
Application number
SE9300156A
Other languages
Swedish (sv)
Other versions
SE9300156L (en
SE500990C2 (en
Inventor
T Sjoequist
Original Assignee
Icl Systems Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Icl Systems Ab filed Critical Icl Systems Ab
Priority to SE9300156A priority Critical patent/SE500990C2/en
Publication of SE9300156D0 publication Critical patent/SE9300156D0/en
Priority to GB9326514A priority patent/GB2274525B/en
Priority to DE19944401017 priority patent/DE4401017A1/en
Priority to FI940287A priority patent/FI103926B1/en
Publication of SE9300156L publication Critical patent/SE9300156L/en
Publication of SE500990C2 publication Critical patent/SE500990C2/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors

Abstract

An arrangement for a personal computer system including an original microprocessor (P2) and an upgrade processor (P1) comprises a bus controller (4) which provides first and second operational modes, the first operational mode being a single processor mode in which only the upgrade processor (P1), which comprises a master upgrade processor, is in operation so that conventional types of adapted software are usable, and the second operational mode being a multiprocessor mode for specially adapted software in which the upgrade processor (P1) acts as a master and the original microprocessor (P2) and any other upgrade processors act as slaves. The bus controller (4) is arranged to provide the single processor mode at start or reset of the personal computer system. Transfer to the multiprocessor mode is controlled by the master upgrade processor (P1) in answer to a program instruction. <IMAGE>
SE9300156A 1993-01-20 1993-01-20 Arrangements in a personal computer system SE500990C2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
SE9300156A SE500990C2 (en) 1993-01-20 1993-01-20 Arrangements in a personal computer system
GB9326514A GB2274525B (en) 1993-01-20 1993-12-29 An arrangement for a computer system
DE19944401017 DE4401017A1 (en) 1993-01-20 1994-01-15 Arrangement of a computer system
FI940287A FI103926B1 (en) 1993-01-20 1994-01-20 Arrangement for connecting an update processor to a microprocessor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE9300156A SE500990C2 (en) 1993-01-20 1993-01-20 Arrangements in a personal computer system

Publications (3)

Publication Number Publication Date
SE9300156D0 true SE9300156D0 (en) 1993-01-20
SE9300156L SE9300156L (en) 1994-07-21
SE500990C2 SE500990C2 (en) 1994-10-17

Family

ID=20388600

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9300156A SE500990C2 (en) 1993-01-20 1993-01-20 Arrangements in a personal computer system

Country Status (4)

Country Link
DE (1) DE4401017A1 (en)
FI (1) FI103926B1 (en)
GB (1) GB2274525B (en)
SE (1) SE500990C2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5490279A (en) * 1993-05-21 1996-02-06 Intel Corporation Method and apparatus for operating a single CPU computer system as a multiprocessor system
EP0803130B1 (en) * 1994-06-29 2007-02-28 Intel Corporation Processor that indicates system bus ownership in an upgradable multiprocessor computer system
DE19701595B4 (en) * 1996-02-15 2004-09-09 Siempelkamp Maschinen- Und Anlagenbau Gmbh & Co. Kg Plant for preheating a mat of pressed material in the course of the production of wood-based panels, in particular chipboard

Also Published As

Publication number Publication date
SE9300156L (en) 1994-07-21
FI940287A (en) 1994-07-21
GB2274525B (en) 1997-01-08
GB9326514D0 (en) 1994-03-02
GB2274525A (en) 1994-07-27
FI940287A0 (en) 1994-01-20
DE4401017A1 (en) 1994-07-21
FI103926B (en) 1999-10-15
FI103926B1 (en) 1999-10-15
SE500990C2 (en) 1994-10-17

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Legal Events

Date Code Title Description
NUG Patent has lapsed