GB2274525A

GB2274525A - Computer system

Info

Publication number: GB2274525A
Application number: GB9326514A
Authority: GB
Inventors: Peter Bertil Sjooquist
Original assignee: ICL System AB
Current assignee: ICL System AB
Priority date: 1993-01-20
Filing date: 1993-12-29
Publication date: 1994-07-27
Anticipated expiration: 2013-12-29
Also published as: GB9326514D0; SE9300156L; FI940287A; GB2274525B; SE9300156D0; FI103926B; SE500990C2; DE4401017A1; FI940287A0; FI103926B1

Description

AN ARRANGEMENT FOR A COMPUTER SYSTEM This invention relates to an

arrangement for a personal computer system including an original, first microprocessor and at least one upgrade processor.

It is often possible to enhance the performance of a personal computer system including one or several processors by inserting a so called upgrade processor.

The upgrade processor has a performance which in some way or another is different from the performance of an original processor. It may be mounted in for instance a personal computer (PC) in order to enhance the personal computer performance. A computer system based on INTEL486" microprocessor often includes a first processor, also called the original processor, at the delivery to a customer, and a socket, called upgrade socket, into which another processor,' called upgrade processor, can be mounted. Thus, the upgrade socket is most often empty at delivery of the personal computer system.

In ordinary computer systems of the kind mentioned above the original processor is shut down once an upgrade processor is installed and cannot be used at the same time as the upgrade processor.

The main object of the invention is to achieve a fast operating computer system in which at least one upgrade processor is installed, but which is completely compatible with a personal computer of the ordinary kind when needed.

Another object is to achieve a powerful personal computer which can be updated with a yet more powerful processor.

According to the present invention there is provided an arrangement for a personal computer system including an original, first microprocessor and at least one upgrade processor, the arrangement comprising a bus controller means for providing first and second operational modes for the personal computer system, the first operational mode being a single processor mode in which only one upgrade processor, which comprises a master upgrade processor, is in operation so that conventional types of adapted software are usable, and the second operational mode being a multiprocessor mode for specially adapted software in which said master upgrade processor acts as a master and the first microprocessor and any other upgrade processors act as slaves, the bus controller means being arranged to provide the single processor mode at start or reset of the personal computer system, and transfer to the multiprocessor mode being controlled by said master upgrade processor in answer.to a program instruction in a computer program fed into the personal computer system.

Thus, in accordance with the invention it is possible to provide multiprocessor features for a computer system having at least one upgrade processor installed.

Also, the invention makes possible a computer system including at least one upgrade processor having multiprocessor features which is fully backwards compatible with a computer system including upgrade processor(s) and not having multiprocessor features.

For a more complete understanding of the present invention and for further objects and advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

Figure 1 is a schematic block diagram of a first embodiment of the arrangement according to the invention, Figure 2 is a schematic diagram of an embodiment of a processor control port register provided in the arrangement according to the invention, Figure 3 is a block diagram of an embodiment of the processor control steering in a logic control in the bus controller in the arrangement according to the invention, and Figure 4 is a block diagram of an embodiment of setting some register bits in the registers in the bus controller.

Referring to Figure 1, in which an upgrade processor Pl, mounted in an upgrade socket, and an original processor P2 in a personal computer (PC) system are connected to a processor bus 1, which includes the data. address and control bus commonly provided in a personal computer. A system board controller 2 having input/output units I/0 connected to some of its inputs and outputs and a main memory 3 are also connected to the processor bus 1. These circuits are common in a personal computer.

In accordance with the invention a bus controller 4 is provided, which also is connected to the processor bus 1. The system board controller 2 has an input/output connected to the processor bus 1 and a control bus directly connected to the bus controller 4.

The bus controller 4 provided in the system in accordance with the invention includes a processor control port PCP including two registers Rl and R2, one for each processor P1 and P2, respectively. The registers R1 and R2 are combined control and status registers, in which at least some of the bits are read only digits, and others function as read/write bits of ordinary kind. Each processor P1 and P2 has an individual bus connected to its individual register Rl and R2, respectively. The bus controller 4 also includes a logic control LC, for instance including a boolean gate array, to perform P2 processor initialization, inter-processor communication, and communication between processors and the system board controller 2, each processor P1 and P2 having an individual bus connected to the logic control LC. The bus controller 4 decides which one of the processors P1 and P2 and the system board controller 2 is to have access to the processor bus 1, and also to have access to the main memory 3.

The system must be compatible with an ordinary PC system. Therefore, the system must be able to operate in the same way as an ordinary PC, when needed. This means that the original processor P2 works in the normal way when no upgrade processor P1 is provided in the upgrade socket.

It also means that there is a possibility to choose between a multiprocessor mode and a single processor mode when the upgrade processor P1 is installed in order to support all single processor operating systems, such as DOS, Windows, SCO UNIX etc. In accordance with the invention the bus co ntroller 4 will control the processors P1 and P2 to take a single processor mode of operation, in which the original processor P2 is shut down, when the computer is energized or after a reset of the system. and to proceed with the processors in this single processor mode until a particular multi-processor mode program instruction in a program fed to the computer gives the instruction to transfer the system into a multi-processor mode of operation, in which the processors act as parts in a multiprocessor system.

In the single processor mode the upgrade processor P1 is the "master" and handles all system interrupts in a totally PC compatible manner.

In multiprocessor mode the upgrade processor takes the part of a master processor, and the original processor P2 becomes a slave processor. ie it does not handle system interrupts any more. As mentioned above, the slave processor P2 is disabled at system start-up, which is compatible with the single processor mode. and the processor P2 must be enabled by the master processor P1 when the multiprocessor mode is demanded. This is done by means of the bus controller 4, as will be apparent below. Also, the arrangement Pl, P2, Rl will react on a specific single processor mode program instruction giving the order to transfer the system from the multiprocessor mode to the single processor mode of operation, when needed.

Processor Control Port A preferred embodiment of the processor control port registers Rl and R2 are shown in Figure 2 and each bit in the registers has the following flag function. The registers R1 and R2 are located at the same address (ie are mapped the same) for both the processors P 1 and P2, and the processor P1 always accesses the register R1. and the processor P2 always accesses the register R2. It is to be noted that these registers function as both control and status registers.

Bit Function 7 Interrupt Enable. INTEN. This bit. when set, enables interrupts generated while using IREQ (see bit 6).

6 Interrupt Requestr IREQ. Writing a 1,111 in this bit generates a pulse generating an inter-processor communication NMI at the other processor. When it is read, this bit indicates the level of the other processor interrupt request signal. "P' means that an interrupt is pending.

Interrupt Acknowledge, IACK. When a 1,111 is written into this bit, an inter-processor communication is generated at the processor connected to this register. When it is read, this bit indicates the level of interrupt request signal for this processor. "P' means that an interrupt is pending.

4 Dual processors, DUAL. This bit is "0" when one processor is installed and I'll, when two processors are installed, ie when an upgrade processor is installed. As a consequence the processor P1 will always read this bit as a '1111 in the register R1, and this bit could then be a read-only bit in R1.

3 P2 Hold, P2HOLD. This bit in the register R1, when cleared (ie is I'V), allows P2 to access the processor bus. P2 can still read data and instructions out of its internal cache memory independently of the setting of this bit. When this bit is set (ie is "V'), P2 is not allowed to access the processor bus. This bit can only be written by Pl. (P2 will always read this bit as a "0" from the register R2).

2 P2 Enable, P2EN. This bit in the register R1, when set (ie is '101'), enables P2 by deasserting UP pin (ie the pin of the original processor P2, which indicates that an upgrade processor is present). When this bit in the register R1 is '1011, the processor P2 is kept in a low power disabled state. This bit is sampled by the bus controller 3 when the P2RESET bit (the bit 0) makes a transition from 1,111 to "0" and should only be changed when the P2RESET bit is "V'. This bit can only be written by the processor P1 (the processor P2 will always read this bit as a 11111 from the register R2).

1 Processor ID, PID. This bit identifies the processor connected to the register and is a read-only bit. R1 has 91011. R2 has 11111.

0 P2 Reset. P2RESET. This bit, when set (ie is "1") in the register Rl, asserts the processor P2 reset signal. The register R2 has a read-only "G".

Processor Control Steering At start or reset of the computer system, the bus controller 4 determines if an upgrade processor P1 is installed and thus available, ie determines which processor is the "master". and routes the PC system signals to the "master" processor.

Only an embodiment of the circuitry in the logic control LC in the bus controller 4 for the processor control steering is shown in Figure 3. Thus. the logic control includes also other circuits for other kinds of control. A number of signals are dependent on whether an upgrade processor P1 is present or not. When it is present there will be a 1,111 in bit No 4 in the register W. When it is not present the bit No 4 in R2 will be "0". Below, the prefix X of a signal name indicates an input or output of the system board controller 2, the prefix PI an input or output of the upgrade processor Pl, and the prefix P2 an input or output of the original processor P2. PyPCPx indicates Processor Control Register bit No x of the processor Py, where y is 1 or 2.

The system board controller 2 provides, as is common in the art the control signals, such as XA20M. XIGNNEO XINTR, XNMI and XCPURST: XA20M being the mask of the physical address bit 20, which is masked before performing a lookup in the internal cache or driving a memory cycle on the processor bus, XIGNNE being a signal indicating that a numerical error shall be ignored, XINTR, maskable interrupt, indicating that an external interrupt has been generated. XNMI, non-maskable interrupt, indicating that a non-maskable interrupt has been generated, and XCPURST being generated by the system board controller 2 as a result of power on or shutdown condition (fatal program failure - recovery failed) detected on the bus 1 by the controller 2 in a conventional manner.

Conventionall:, the signal XCPURST could also be activated by the keyboard controller, but in the device according to the invention clearing of the processor control port PCP is not wanted. Processor reset using the keyboard controller is therefore not supported in the device according to the invention.

All the signals XA20M, XIGNNE and XINTR shall be provided directly via the logic control LC to the processor P1 as inputs P1A20M, PlIGNNE and PlINTR to control P1 when it is present in the system. Thus, the following VHDL expressions are valid:

P1A20m ≤ XA20M PlIGNNE ≤ XIGNNE PlINTR ≤ XINTR The signals XA20M, XIGNNE, XINTR must be provided to the original processor P2 when no upgrade processor P1 is present, which is indicated by 11011 in bit No 4 in the register R2. A "1" in this bit indicates that an upgrade processor P1 is present. Therefore, a first AND-gate Al having an inverting input connected to the bit No 4 in register R2 and a non- inverting input connected to the line XA20M has its output connected to the original processor P2. Then, the output provides the signal P2A20M only when the bit No 4 in the register R2 is "0" and XA20M is '1111, ie when no upgrade processor P1 is provided. Accordingly a second AND-gate A2 has an inverting input connected to the bit No 4 in R2 and a non- inverting input to the line XIGNNE for providing the output P21GNNE, and third AND-gate A3 has an inverting input connected to the bit No 4 in R2 and a non-inverting input to the line XINTR for providing the output P21NTR. Thus, the following VHDL expressions are valid:

P2A20M ≤ not DUAL and XA20M P21GNNE ≤ not DUAL and XIGNNE P21NTR ≤ not DUAL and XINTR An input PlMI should be provided when an output XNMI is fed from the controller 2 and also when the bit No 6 in the register P2 and the bit No 7 in the register Rl have a 11111. Therefore, these bits are connected to the two non-inverting inputs of an AND-gate A4, and the output of the gate A4 and the output XNMI are fed to inputs of an OR-gate OR1. The output of the OR-gate feeds the signal PlMI to the processor P1 in accordance with the following VHDI, expression:

PlMI ≤ XNMI or (P2PCP6 and P1PCP7) The signal XNMI shall be fed to the processor P2, when no upgrade processor is present, and also when the bit No 6 in the register R1 and the bit No 7 in the register R2 have a "P'. Therefore, these bits are connected to the two non-inverting inputs of an AND-gate A6. The output XNMI is fed to a non-inverting input of an AND-gate AS and the bit No-4 in the register R2 is fed to an inverting input of the AND-gate AS. The outputs of the AND-gates AS and A6 are fed to one input each of and OR- gate OR2. The output of the OR-gate OR2 feeds the signal MMI to the processor P2 in accordance with the following VDL expression:

MMI ≤ (not DUAL and XNMI) or (P1PCP6 and P2PCP7) The output XCPURST is to be provided to both the processors P1 and P2. It is also to be provided to the processor P2 when the bit No 0 in the register Rl is "P'. as will be described below. Therefore the output XCPURST of the controller 2 is fed directly via the logic control LC as the input P1CPURST to the processor P1, ie P1CPURST≤XCPURST. The bit No 0 in R1 is fed to one input and XCPURST to another input of an OR-gate OR3. The output of the OR-gate OR3 then feeds the input P2CPURST to the processor P2 in accordance with the following VHDI, expression:

P2CPURST ≤ XCPURST or P1PCPO The input XFERR (floating point error) to the controller 2 will be provided by the processor P1 when an upgrade processor is present or by the processor P2 when no upgrade processor is present. Therefore, the bit No 4 of register R2 is connected to a non-inverting input of an AND-gate A7 and to an inverting input of an AND-gate A8. An output P1FERR from the processor P1 is fed to another non-inverting input of the AND-gate A7. and output P2FERR from the processor P2 is fed to another non-inverting input AND-gate A8. The outputs of the AND-gates A7 and A8 are fed to an input each of an OR-gate OR4. The output of the OR-gate OR4 then feeds the signal XFERR to the controller 2 in accordance with the following VHDI, expression:

XFERR ≤ (DUAL and P1FERR) or (not DUAL and P2FERR) As apparent above the circuitry in Figure 3 is easily provided once the VHDI, expressions are know. Below, VHDI, expression representations of the same kind as above will be given instead of having the circuitry in the logic control outlined in Figures.

Upgrade Processor Detection At each processor reset, caused by the XCPURST signal, the bus controller 2 determines if a processor is fitted into the upgrade socket. This is done by asserting a signal P1HOLD from the socket of the processor P1 during reset and if a signal P1HOLDA from the socket of the processor P1 is received the upgrade processor P1 is present in the socket. If no signal P1HOLDA is received the upgrade processor is not provided in its socket. The DUAL bit No 4 in the register R2 is then set 11111.

In systems when the upgrade processor P1 supports the MP# pin, it is sufficient to set the DUAL bit if MP# is low.

Processor Control Port However, one more example of a circuit will be given in Figure 4. It gives an example of how some of the bits in the registers Rl and R2 are implemented. A signal write P21NTEN is provided by the logic control and fed to an input of a controllable buffer Bl. When the buffer receives a control signal from the processor P2 that the bit No 7 in the register R2 is to be read, the buffer sets this bit on the data bus as data bus line D7. The elements A6 and OR2 are the same as the ones shown in Figure 3. In Figure 3 it is shown that P2PCP7 could be provided as one of the inputs to the AND-gate A6. The other input of the AND-gate A6 could be provided from a bistable SR latch M1, which is set by a pulse IREQ (P1PCP6, bit No 6 in the register Rl for the processor P1) and the reset by a pulse IACK (P2PCPS, bit No 5 in the register R2 for the processor P2). Thus it is shown in Figure 4 that it is the signals P21NTEN, IREQ as they are present in the logic control which control the AND-gate A6. The output IREQ of the SR latch M1 is fed to an input of a buffer B2 controllable by the processor P1 and is transferred to the address bus as data bus line D6, when the processor P1 demands reading of the bit No 6 in the register R1. The output IREQ of the SR latch M1 is also fed to an inverting input of a buffer B3f which feeds the signal on its input to the data bus line DS, when the processor P2 provides a signal for reading the bit No 5 in the register R2.

Differences between the Processors in Multiprocessor Mode The processors P1 and P2 appear in the same way to the main memory 3 and to the I/0 subsystem connected to the system controller 3. However, the following differences exist between the processors in multi- processor mode:

Bus Priority The processor P1 has a higher priority than the processor P2. When P1 needs the processor bus 1, and the processor P2 is the momentary owner of it, then the processor P2 is requested to get off the bus immediately, which is made by activating the P2HOLD signal in the bit No 3 in the register R1. When the processor P2 needs the bus the bus controller 3 will delay requesting the bus until the processor P1 has no internal request left for the bus. This assures that the processor P1 will get a larger portion of the available bus bandwidth.

Arbitration between the processor Pl. the processor P2 and the controller 2 is performed by using bus request P1BREQt hold request P1HOLD and hold acknowledge P1HOLDA signals from the processor P1 and bus request P2BREQ, hold request P2HOLD and hold acknowledge P2HOLDA signals from the processor P2 and hold request XHOLD and hold acknowledge XHOLDA signals from the controller 2 to the logic control LC. The following state machine (VHM expression) shows how the arbitrations works. Wait until the clock pulse is 1,111.

When the processor P1 is the owner of the bus 1 then:

P1HOLD ≤ XHOLD or (P2BREQ and not P1BREQ) P2HOLD ≤ 11111 XHOLDA ≤ XHOLD and P1HOLDA If XHOLD="1" and P1HOLDA='1111 then the next state will be that the controller 2 is the owner of the bus 1. Otherwise if P2BREQ="1" and P1BREQ=11011 and P1HOLDA="V' then the next state will be that the processor P2 is the owner of the bus 1.

When the processor P2 is the owner of the bus 1 then:

P1HOLD ≤ I'P' P2HOLD ≤ XHOLD or P1BREQ XHOLDA ≤ XHOLD and P2HOLDA If XHOLD="P' and P2HOLDA="P' then the next state will be that the controller 2 is the owner of the bus 1. Otherwise if P1BREQ="1" and P2HOLDA="1" then the next state will be that the processor P1 is the owner of the bus 1.

When the controller 2 is the owner of the bus 1 then:

P1HOLD ≤ "I" P2HOLD ≤ 11111 XHOLDA ≤ 11011 If XHOLD="011 and if DUAL="O'I or (P2BREQ="P' and P1BREQ="C) then the next state will be that the processor P2 is the owner of the bus 1. Otherwise the processor P1 will be the owner.

If no upgrade processor P1 is present P1BREQ is "011 due to a pulldown resistor (not shown) connected to the socket pin for that signal for the processor Pl. P1HOLDA is 11P due to a pullup resistor (not shown). This will effectively case the empty socket for an upgrade processor not to participate in any arbitration.

As can be seen from the VHDI, expressions above, the arbiter function in the bus controller 4 assign s the highest priority to the system board controller 2, next highest priority to the processor P1 and the lowest priority to the processor P2. Both the processors P1 and P will park on the processor bus 1, when they are the owner of it, until another device requests the bus 1. The system bus controller 2 will not park on the bus, since control will be given back to the processor P1 or the processor P2 immediately. This will assure PC compatibility when the system is running in single processor mode and allows for maximum utilization of the bus 1.

Processor Control Port Access The bits 3 and 2 in the register R1 are only writable by control from the processor Pl. These bits control the enabling and initialization of the processor P2.

P1 Interrupt Handling The processor P1 receives all hardware interrupts from the system board controller 2. The inter-processor communication NMI (Non-Maskable Interrupt) (generated by the processor P2 using its IREQ bitt ie bit No 6 in the register R2) is shared by other signals in the system, such as XNMI cause by parity errors and the IOCHK-signal from the system bus. The P1NMI-handler (not shown but a standard module in a microprocessor of the type Intel486" suitable for the invention) of the processor P1 must read the bit 5, IACK, in the register R1 to determine the source of the NMI. If the source of the NMI was an inter-processor NMI, the NMI handler for the processor P1 must write a 11111 in the bit No 5, IACK, before returning. in order to remove the pending NMI request.

P2 Interrupt Handling The processor P2 does not receive any hardware interrupts from the system board controller 2. The only interrupt received by the processor P2 is the inter-processor communication NMI generated by the processor Pl. The P2NMI-handler of the processor P2 must set the bit 5, IACK, in the register R2 to remove the NMI request before returning.

Reset Both the processors P1 and P2 are reset by a signal XCPURST from the system board controller 2 fed to the bus controller 4, which clears the processor control port PCP, ie sets in an initial condition via the logic control LC.

The original processor P2 can also be reset by the upgrade processor P1 using the P2RESET bit in the register Rl. However, it is to be noted that the processor P2 cannot reset processor Pl.

Thus, whenever the signal XCPURST is fed to the bus controller 4 from the system board controller 2, then the processor P2 is disabled and possible interrupts are cancelled.

Gate A20 The gate A20 logic in the system control 2 will only affect the processor Pl.

Initialization of the Processor P2 in Multiprocessor Mode A BIOS (Basic Input Output System) start-up code from the system board controller 2 contains support for starting the processor P2. If BIOS start-up code detects multiprocessor mode (the bit No 4 DUAL in R2 is 'Ill') and the current processor is P2 (PID is 11111 in bit No 1 in R2), BIOS will jump to the address contains in its memory cell 467. The processor P1 will run through the normal BIOS start-up code.

To initialize the processor P2 in multiprocessor mode the system software could for example perform the following steps:

1. Write the start address for the processor P2 into the 32-bits data cell (DWORD) at the physical address 467; 2. Place the processor P2 in a reset condition by setting the bit No 0 in the register Rl, P2RESET; 3. Enable the processor P2 by setting the bit No 2 in the register Rl, P2EN; 4. Wait for the minimum reset time, which often is at least 0.1 PS; 5. Inactivate the reset for the processor P2 by clearing the bit No 0 in the register Rl, P2RESET.

The processor P2 will start executing the BIOS start-up code and jump to the physical address 467. Note that the processor P2 will not start executing if it is placed in hold by the processor P1 using the P2HOLD bit in the register Rl.

Normally the processor P2 will indicate that it has started executing by setting a semaphore as its first operation. The processor P1 will, after inactivating the bit P2RESET in R1. wait for this semaphore to assure that the processor P2 has started successfully (see the flag function for bit No 5 above).

Multi-processor Communication The processors P1 and P2 can communicate by using at least two methods. The multiprocessor communication is made by a program, and this program can be written in many different ways. Therefore, the description below gives the general lines of direction of how this programming can be done.

The first method uses semaphores in shared memory (all memories are shared). TEST - AND - SET program instructions are used to perform atomic operations on the semaphores. This method is preferred when handling common data structures and is normally used by the operating system core.

The second method uses the inter-processor NMI to indicate that a message is available in shared memory.

The inter-processor NMI handshaking method can be used for any processor communication but is mainly provided to support distributed interrupts among the two processors. Since the processor P1 will receive all interrupts from the system board system 2, such as XINTR and XNMI, it must determine which interrupt to process itself and which interrupt to assign to the processor P2. If the processor P1 determines that an interrupt should be assigned to the processor P2. it will first check if the processor P2 is currently running a higher priority interrupt handler.

If that is the case the processor P1 will just mark the interrupt as pending for the processor P2. If the processor P2 can be interrupted, the processor P1 will write a message indicating what interrupt to serve and interrupt the processor P2 (for instance by setting the bit No 6 in the register R2 to 11111, or by making it possible to set this bit via a buffer) when this bit is read by the processor P2. The P2M handler will detect that the processor P2 is running, read the message and start executing the interrupt service routine. When this is completed. the processor P2 will check for any pending interrupts, and if so service those interrupts.

Interrupts distributed this way can support interrupt service routines written for multiprocessor architectures using hardware interrupt distribution. This is done by revectoring all hardware interrupts letting the processor P1 have control before the actual service routine is called. The processor P1 can then determine which of the processors shall execute the service routine effectively emulating the hardware distribution mechanism.

In the embodiment of the invention given above only one upgrade processor is shown and discussed. However, it could be possible to provide more than one upgrade processor in a system in accordance with the invention, evenif the control of them would be quite complicated. In such a system only one of the upgrade processors can act in single processor mode. In multiprocessor mode, however, all the processors in the system could be given a particular priority order, and the system will be acting as a multiprocessor system with several processors. Naturally. the bus controller 4 has one register for each of the processors in the system.

d

Claims

1. An arrangement for a personal computer system including an original, first microprocessor and at least one upgrade processor, the arrangement comprising a bus controller means for providing first and second operational modes for the personal computer system, the first operational mode being a single processor mode in which only one upgrade processor, which comprises a master upgrade processor, is in operation so that conventional types of adapted software are usable, and the second operational mode being a multiprocessor mode for specially adapted software in which said master upgrade processor acts as a master and the first microprocessor and any other upgrade processors act as slaves, the bus controller means being arranged to provide the single processor mode at start or reset of the personal computer system, and transfer to the multiprocessor mode being controlled by said master upgrade processor in answer to a program instruction in a computer program fed into the personal computer system.

2. An arrangement according to Claim 1, wherein said bus controller means includes a respective register for each multiprocessor and processor connectable in said computer system, each register serving as a control port for the microprocessor and processor connected to it, said registers containing various functions needed to perform initialization for the microprocessor or processors in the system functioning as slave processors and inter-processor communication.

3. An arrangement according to Claim 1 or Claim 2, wherein the bus controller means includes a logic control including a boolean gate array providing logic control of the microprocessor and processors, the registers and of a system board controller means connected to the system.

4. An arrangement according to any one of the preceding Claims, wherein the master upgrade processor, when the system is in the multiprocessor mode, reacts on a specific single processor mode program instruction giving the order to transfer the system from the multiprocessor mode to the single processor mode of operation.

5. An arrangement according to Claim 2, or Claim 3 or Claim 4 as appendant to Claim 2, wherein the registers are combined control and status registers.

6. An arrangement according to Claim 2, Claim 5, or Claim 3 or Claim 4 as appendant to Claim 2, wherein the registers are located at the same address for the multiprocessor and processors, and the one upgrade processor always accesses its respective register, and the first microprocessor always accesses its respective register.

7. An arrangement according to any one of Claims 2, 5 and 6, or Claim 3 or Claim 4 as appendant to Claim 2, wherein in the registers one of the bits (INTEN). when set, enables interrupts generated while using another of the bits (IREQ), wherein when a 11111 is written into said another bit there is generated a pulse generating an inter-processor communication interrupt at the register belonging to another of the microprocessor and processors, and wherein when said another bit is read there is indicated the level of interrupt request signal for this another microprocessor or processor.

8. An arrangement according to any one of Claims 2, 51 6 and 7, or Claim 3 or Claim 4 as appendant to Claim 2, wherein only one upgrade processor is provided, and wherein a dual-bit in the register for the first microprocessor is "0" when one processor is installed and 11111 when two processors are installed.

9. An arrangement according to any one of Claims 2, 5, 6, 7 and 8, or Claim 3 or Claim 4 as appendant to Claim 2, wherein there is a first microprocessor hold-bit in the register for the master upgrade processor which when cleared (ie is 11011) allows the first microprocessor to access a processor bus and when set (ie is 11111) prohibits access of the first microprocessor to the processor bus.

10. An arrangement for a personal computer system substantially as herein described with reference to and as illustrated in the accompanying drawings.