SE500990C2 - Arrangements in a personal computer system - Google Patents

Abstract

An arrangement for a personal computer system including an original microprocessor (P2) and an upgrade processor (P1) comprises a bus controller (4) which provides first and second operational modes, the first operational mode being a single processor mode in which only the upgrade processor (P1), which comprises a master upgrade processor, is in operation so that conventional types of adapted software are usable, and the second operational mode being a multiprocessor mode for specially adapted software in which the upgrade processor (P1) acts as a master and the original microprocessor (P2) and any other upgrade processors act as slaves. The bus controller (4) is arranged to provide the single processor mode at start or reset of the personal computer system. Transfer to the multiprocessor mode is controlled by the master upgrade processor (P1) in answer to a program instruction. <IMAGE>

Description

15 20 25 30 35 ..,. ' The main object of the invention is achieved with an arrangement of the type stated in the characterizing part of the appended claim 1. Further features and further developments of the arrangement according to the invention are stated in the other patent claims.

Thus, in accordance with the invention, it is possible to achieve multiprocessor characteristics of a computer system having at least one upgraded processor installed.

In addition, the invention provides a computer system comprising at least one upgrade processor, which system has multiprocessor characteristics and which is entirely compatible with a computer system comprising one or more upgrade processors and which does not have multiprocessor characteristics.

Brief Description of the Figures The invention is described in more detail below with reference to the accompanying drawings, in which Figure 1 is a schematic block diagram of a first embodiment of the arrangement according to the invention, Figure 2 is a schematic diagram of an embodiment of a processor controlled register arranged in the arrangement according to the invention, figure 3 is a block diagram of an embodiment of the control of the processor control in a logic control device in the bus control unit in the arrangement according to the invention, and figure 4 is a block diagram of an embodiment for putting some register bits in the registers in the bus control unit. 10 15 20 25 30 35 500 990 3 Register bits in the registers in the bus control unit.

In Figure 1, where an upgrade processor P1, mounted in an upgrade socket, and an original processor P2 in a personal computer system (PC) are connected to a processor bus 1, which includes the data, address and control bus, which is usually arranged in a personal computer. A system board controller 2 with input / output units I / O connected to some of its inputs and outputs and a main memory 3 are also connected to the processor bus 1. These circuits are common in a personal computer.

According to the invention, a bus control unit 4 is provided, which is also connected to the processor bus 1. The system card control unit 2 has an input / output connected to the processor bus 1 and a control bus connected directly to the bus control unit 4.

The bus control unit 4 arranged in the system according to the invention comprises a processor control port PCP comprising two registers R1 and R2, one for each processor P1 and P2, respectively. The registers R1 and R2 are combined control and status registers, in which at least some of the bits are fixed digits (ie digits that can only be read), and others function as locks / write bits of ordinary kind. Each processor P1 and P2 has an individual bus connected to its individual register R1 and R2, respectively. The bus controller 4 also includes a logic controller LC, for example comprising a Boolean gate circuit, for effecting initiation of the processor P2, communication between the processors, and communication between the processors and the system board controller 2, each processor P1 and P2 has an individual bus connected to the logic control device LC. The bus control unit 4 determines which of the processors P1 and P2 and the system card control unit 2 is to have access to the processor bus 1 and also to have access to the main memory 3.

The system must be compatible with an ordinary PC system.

Therefore, the system must work in the same way as an ordinary PC, when needed. This means that the original processor P2 10 15 20 25 30 4 operates in the normal way, when no upgrade processor P1 is placed in the upgrade socket.

It also means that there is a possibility to choose between a multiprocessor mode and a single processor mode, when the upgrade process P1 is installed, to support all single processor operating systems, such as DCS, Windows, SCO, UNIX etc. According to the invention, the bus controller 4 will control the processors P1 and P2 to adopt a single processor mode of operation in which the original processor P2 is disconnected when the computer is turned on or after a reset of the system, and to continue with the processor in this single processor mode until a special multiprocessor mode program instruction in a program entered into the computer instructs to transfer the system to a multiprocessor operating mode, in which the processors operate as parts of a multiprocessor system.

In single processor mode, the upgrade processor P1 is the parent processor and handles all system outages in a fully PC-compatible manner. In the multiprocessor mode, the upgrade processor assumes the role of a parent processor, and the original processor P2 becomes a slave processor, ie it no longer handles system failures. As stated above, the slave processor P2 is blocked at system startup, which is compatible with single processor mode, and processor P2 must be opened by the parent processor P1, when multiprocessor mode is requested. This is done by means of the bus control unit 4, as will be clarified below. In addition, the arrangements P1, P2, R1 will respond to a special program instruction for single processor mode, which gives orders to transfer the system from the multiprocessor working mode to the single processor working mode, when needed. 10 15 20 25 30 500 99Ü LH Processor control port A preferred embodiment of the processor control port registers R1 and R2 is shown in Figure 2, and each bit in the registers has the following flag function. The registers R1 and R2 are located at the same address (ie are channeled in the same way) for both processors P1 and P2, and the processor P1 always has access to the register R1, and the processor P2 always has access to the register R2. It should be noted that these registers function as both control and status registers.

Bit: ___ ~ I Function Activate interrupt, NONE. This bit, when set, activates interrupts generated using IREQ (see bit 6).

Interruption request, IREQ. Entering an "I" in this bit generates a pulse, which generates an intermediate processor communication NMI at the other processor. When locked, this bit indicates the level of the interrupt request signal for the other processor. "l" means that an interruption is just in progress.

Interruption receipt, IACK. When an "1" year is written in this bit, an intermediate processor communication is generated at the processor connected to this register. When locked, this bit indicates the level of the interrupt request signal for this processor. "l" means that an interruption is just in progress.

Dual processors, DUAL. This bit is "0" when a processor is installed, and "1" when two processors are installed, ie when an upgrade processor is installed. Therefore, the processor P1 will always read this bit as an "I" in the register R1, and this bit could then be a fixed bit in R1.

Hold P2, PZHOLD. This bit in register R1, when set to zero (ie is "0"), allows P2 to access the processor bus. P2 can still read data and instructions from its internal cache regardless of whether this bit is set or not. When this bit is set (ie is "1"), P2 is not allowed to access the processor bus. This bit can only be written by P1. (P2 will always read this bit as a "0" from register P2).

Activate P2, PZEN. This bit in register R1, when set (ie is "1"), activates P2 by not claiming the UP pin (ie the pin of the original processor P2, which indicates that an upgrade processor is installed). When this bit in the register R1 is "0", the processor P2 is kept in a disabled state with low power. This bit is sampled by the bus controller 3, when the bit PZRESET (bit 0) makes a transition from "1" to "0" and should only be changed when the bit PZRESET is "1". can only be written by the processor P1 (the processor P2 This bit will always read this bit as a "1" from the register R2).

Processor ID, PID. This bit identifies the processor connected to the registry and is a fixed bit.

R1 has "0". R2 has "1". Reset P2, PZRESET. This bit, when set (ie year "1") in the register R1, claims the reset signal of the processor P2. The register R2 has a fixed "0". When starting or resetting the computer system, the bus controller 4 determines if an upgrade processor P1 is installed and thus available, i.e. determines which processor is the parent, and directs the PC system signals to the parent processor.

Only the embodiment of the circuit arrangement in the logic control device LC in the bus control unit 4 for controlling the processor control is shown in Figure 3. Thus, the logic control device also comprises other circuits for other types of control. A number of signals depend on whether or not an upgrade processor P1 is present. When it exists, there will be a "1" in bit # 4 in register R2. When not present, bit # 4 in R2 is "0". Below, the prefix X in a signal name indicates an input or output of the system board controller 2, the prefix P1 an input or output of the upgrade processor P2 and the prefix P2 an input or output of the original processor P2. PyPCPx indicates the processor control register bit no. X for the processor Py, where y is 1 or 2.

The system card controller 2 provides, as is usual in this part of the art, the control signals, such as XA20M, XIGNNE, XINTR, XNMI and XCPURST, where XAZOM is the mask of the physical address bit 20, which is masked before performing a search in the internal cache. or driving a memory cycle on the processor bus, XIGNNE is a signal indicating that a numerical error should be ignored, XINTR, maskable interrupt, indicating that an external interrupt has been generated, XNMI, non-maskable interrupt, indicates that a non-maskable interrupt has been generated, and XCPURST is generated by the system board controller 2 as a result of power on or down state (fatal program error - recovery failed) detected on bus 1 by controller 2 in conventional manner. In a conventional manner, the signal XCPURST could also be activated by the keyboard control unit, but in the device according to the invention erasure of the processor control port PCP is undesirable. Processor reset using the keyboard controller is therefore not supported in the device according to the invention.

All signals XAZOM, XIGNNE and XINTR shall be provided directly via the logic controller LC to the processor P1 such as input signals P1A20M, PIIGNNE and PIINTR to control P1, when present in the system. Thus, the following VHDL expressions are valid.

PlA20M <= XAZOM PIIGNNE <= XIGNNE PIINTR <= XINTR The signals XAZOM, XIGNNE, XINTR must be given to the original processor P2 when no upgrade processor P1 is connected, which is indicated by "0" in bit no. 4 in register R2. An "1" in this bit indicates that an upgrade processor P1 is connected. Therefore, a first AND gate A1 with an inverted input connected to bit No. 4 in the register R2 and a non-inverted input connected to the line XAZOM has its output connected to the original processor P2. Then the output gives the signal P2A20M only, when bit no. 4 in the register 2 is "0" and XA20M is "1", ie when no upgrade processor P1 is provided. Accordingly, a second AND gate A2 has an inverted input connected to bit No. 4 in R2 and a non-inverted input to the line XIGNNE to provide the output signal PZIGNNE, and a third AND gate A3 has an inverted input connected to bit no. 4 in R2 and a non-inverted input to the line XINTR to provide the output signal PZINTR. Thus, the following VHDL expressions are valid: P2A2OM <= non-DUAL and XA2OM PZIGNNE <= non-DUAL and XIGNNE PZINTR <= non-DUAL and XINTR 10 15 20 25 30 35 500 990 9 An input signal to PINMI should be given when an output signal XNMI is supplied from the control unit 2, and also when bit no. 6 in the register P2 and bit no. 7 in the register R1 have a "1". Therefore, these bits are connected to the two non-inverting inputs on an AND gate A4, and the output signal of the gate A4 and the output signal XNMI are fed to the inputs of an OR gate OR1. The output of the OR gate supplies the signal PINMI to the processor P1 in accordance with the following VHDL expression: PINMI <= XNMI or (P2PCP6 and PIPCP7) The signal XNMI shall be supplied to the processor P2, when there is no upgrade processor, and also when bit no. in register R1 and bit no. 7 in register R2 has a "1". Therefore, these bits are connected to the two non-inverting inputs on an AND gate A6, and the output signal from the AND gate A6 and the output signal XNMI are fed to a non-inverting input on an AND gate A5, and bit no. 4 in register R2 is fed to an inverting input on AND gate A5. The output signals from the AND gates are fed to their respective inputs on an AND gate OR2. The output signal from the OR gate OR2 supplies the signal P2NMI to the processor 2 according to the following VHDL expression.

PZNMI <= (not DUAL and XNMI) or (PlPCP6 and PZPCP7) The output XCPURST should be given to both processors P1 and P2. It shall also be given to the processor P2, when bit no. 0 in the register R1 is "1", as will be described below. Therefore, the output signal XCPURST of the control unit 2 is fed directly via the logic control device LC such as the input signal PICPURST to the processor P1, i.e. PICPURST <= XCPURST. Bit No. 0 in R1 is fed to one input and XCPURST to another input on an OR gate OR3. The output signal of the OR3 gate then supplies the input signal PZCPURST to the processor P2 in accordance with the following VHDL expression: P2CPURST <= XCPURST or PIPCPO 10 15 20 25 30 35 500 990 N The input signal XFERR (floating point error) to the control unit 2 will be given by the processor P1, when an upgrade processor is present, or by the processor P2, when no upgrade processor is present. Therefore, bit 4 is connected to a non-inverting input on an AND gate A7 and to an inverting input on an AND gate A8. An output signal PIFERR from the processor P1 is supplied to a second non-inverting input on the AND gate A7, and an output signal PZFERR from the processor P2 is supplied to a second non-inverting input on the AND gate A7. The output signals from AND gates A7 and A8 are fed to their respective inputs on an OR gate OR4. The output signal from the OR gate OR7 then supplies the signal XFERR to the control unit 2 in accordance with the following VHDL expressions: XFERR <= (DUAL and PIFERR) or (not DUAL and PZFERR) As is clear from the above, the circuit arrangement in Figure 3 is light. achieved, once the VHDL expressions are known. Below, VHDL expression representations of the same kind as above will be given instead of having the circuit arrangements in the logic control device drawn in figures.

Upgrading processor detection At each processor reset, caused by the XCPURST signal, the bus controller 2 determines if a processor is inserted in the upgrade socket. This is done by claiming a signal PIHOLD from the socket of the processor P1 during reset, and if a signal PIHOLDA from the socket of the processor P1 is received, the upgrade processor P1 is in the socket. If no signal PIHOLDA is received, the upgrade processor is in its socket. Bit No. 4, DUAL, in register R2 is then set to "1".

In systems where the upgrade processor P1 carries the MP # pin, it is sufficient to set the DUAL bit, if MP # is low. 10 15 20 25 30 500 990 ll The processor control port Another example of a circuit will, however, be given in Figure 4. It gives an example of how some of the bits in registers R1 and R2 are implemented. A signal write PZINTEN is given by the logic controller and fed to an input of a controllable buffer circuit B1. When the buffer circuit receives a control signal from the processor P2 that bit no. 7 in the register R2 is to be read, the buffer circuit sets this bit on the data bus such as the data bus line D7. Elements A6 and A7 are the same as those shown in Figure 3. Figure 3 shows that PZPCP7 could be arranged as one of the inputs to the AND gate A6.

The second input of the AND gate A6 could be given from a bistable SR holding circuit M1, which is set with a pulse IREQ (P1PCP6, bit no. 6 in the register R1 for the processor P1) and reset by a pulse IACK (P2PCP5, bit no. 5 in register R2 for processor P2). Thus, Figure 4 shows that it is the signals PZINTEN, IREQ as it is present in the logic control circuit, which control the AND gate A6. The output signal IREQ from the SR hold circuit M1 is fed to an input of a buffer circuit 82, which is controllable by the processor P1, and is transmitted to the address bus as the data bus line D6, when the processor P1 reads bit 6 in the register R1. The output signal IREQ from the SR holding circuit M1 is also fed to an inverting input of a buffer circuit B3, which supplies the signal at its input to the data bus line D5, when the processor P2 gives a signal to read bit no. 5 in the register R2.

Differences between the processors in multiprocessor mode The processors P1 and P2 behave in the same way in relation to the main memory 3 and the I / O subsystem connected to the system control unit 3. However, there are the following differences between the processors in multiprocessor mode: 10 15 20 25 30 35 sno 99-0 12 Bus priority The processor P1 has a higher priority than the processor P2. When P1 needs the processor bus 1, and the processor P2 is the instantaneous owner of it, then the processor P2 is requested to get off the bus immediately, which is done by activating the PZHOLD signal in bit no. 3 in the register R1. When the processor P2 needs the bus, the bus controller 3 will wait to request the bus until the processor P1 has no internal request left for the bus. This ensures that the processor P1 will receive a larger share of the available bus bandwidth.

Mediation between the processor P1, the processor P2 and the control unit 2 is performed by using the bus request signal PIBREQ, the hold request signal PIHOLD and the hold acknowledgment signal PIHOLDA from the bus P1 and the bus request signal PZBREQ, the hold request signal PZHOLD and the hold acknowledgment signal P The following machine condition (VHDL expression) shows how the mediators work. Wait until the clock pulse is "l".

When the processor P1 is the owner of the bus 1 then applies: PIHOLD <= XHOLD or (PZBREQ and not PIBREQ) PZHÛLD <= "I" XHOLDA <= XHOLD 0Ch PIHOLDÄ If XHOLD = "l" and PlHOLDA = "l" then the next state comes to be, that the control unit 2 is the owner of the bus 1. Otherwise, if P2BREQ = "1" and P1BREQ = "0" and P1HOLDA = "1", the next condition will be that the processor P2 is the owner of the bus 1. 20 25 30 35 500 990 13 When the processor P2 is the owner of the bus l then the following applies: PIHOLD <= "l" P2HOLD <= XHOLD or PIBREQ XHOLDA <= XHOLD and PZHOLDA If XHOLD = "l" and P2HOLDA = "l", the next condition to be that the controller 2 is the owner of the bus, otherwise, if P1BREQ = "1" and P2HOLDA = "1", the next condition will be that the processor P1 is the owner of the bus 1.

When the control unit 2 is the owner of the bus 1, the following applies: PIHOLD <= "l" PZHOLD <= "I" XHOLDA <= "O" If XHOLD = "O" and if DUAL = "0" or (P2BREQ = "l" and PlBREQ = "0"), the next condition will be that the processor P2 is the owner of the bus 1. Otherwise, the processor P1 will be the owner.

If no upgrade processor P1 is present, PIBREQ is "0" due to a disconnect resistor (not shown) connected to the socket pin for this signal for the processor P1. PIHOLDA is "I" due to a voltage resistance (not shown).

This will effectively cause the empty socket for an upgrade processor to not participate in any mediation.

As can be seen from the above VHDL expressions, the storage function in the bus controller 4 assigns the highest priority to the system board controller 2, the second highest priority to the processor P1 and the lowest priority to the processor P2. Both processors P1 and P2 will park on the processor bus 1, when they own it, until another device requests the bus 1. The system bus controller 2 will not park on the bus, as control will be given back to the processor P1 or processor P2 immediately- 10 15 20 25 30 35 990 14 bart. This will ensure PC compatibility, when the system is running in single processor mode and allow maximum use of the bus 1.

Access to processor control port Bits 3 and 2 in register R1 can only be written by control from processor P1. These bits control the activation and initialization of the processor P2.

Interrupt management for P1 The processor P1 receives all hardware interruptions from the system port controller 2. The communication between the processors NMI (Non-Maskable Interrupt) (generated by processor P2 using its IREQ bit, ie bit no. 6 in register R2) is divided by other signals in system, such as XNMI caused by parity errors and the IOCHK signal from the system bus. The PINMI handler (not shown but a standard module in an Intel486m microprocessor suitable for the invention) of the processor P1 must read bit No. 5, IACK, in register R1 to determine the source of the NMI signal. If the source of the NMI signal was an NMI signal for communication between the processors, the NMI handler for the processor P1 must write a "1" in bit No. 5, IACK, before retransmission, in order to remove the current NMI request.

Interrupt management for P2 The processor P2 does not receive any hardware interruptions from the system board controller 2. The only interrupt signal received by the processor P2 is the communication between the processors NMI generated by the processor 1. Processor P2 The P2NMI handler must put bit # 5, IACK, in register R2 to remove the NMI capability before retransmission. Reset Both processors P1 and P2 are reset by a signal XCPURST from the system board controller 2 fed to the bus controller 4, which clears the processor controller board PCP, i.e. puts it in an initial state via the logic controller LC.

The original processor P2 can also be reset by the upgrade process P1 using the PZRESET bit in register R1. It should be noted, however, that the processor P2 cannot reset the processor P1.

Thus, whenever the signal XCPURST is fed to the bus controller 4 from the system board controller 2, the processor P2 will be activated, and possible interruptions will be inhibited.

Gate A20 The logic of gate A20 in system controller 2 will only affect processor P1.

Initializing processor P2 in multiprocessor mode A Basic Input Output System (BIOS) code from the system board controller 2 provides support for starting processor P2. If the BIOS boot code detects multi-processor mode (bit no. 4 DUAL in R2 is "1") and the current processor is P2 (PID is "I" in bit no. Li R2), the BIOS will jump to the address which is located in memory cell 467. Processor P1 will run through the normal BIOS boot code.

To initialize processor P2 in multiprocessor mode, for example, the system software could perform the following steps: 1. Enter the start address of processor P2 in the 32-bit data cell (DWORD) at the physical address 467; 10 15 20 25 30 35 500 990 16 2. place the processor P2 in a reset state by putting bit no. 0 in the register R1, PZRESET; 3. activate the processor P2 by putting bit no. 2 in the register R1, P2EN; 4. wait for the minimum recovery time, which is often at least 0.1 us; 5. deactivate the reset of the processor P2 by emptying bit no. 0 in the register R1, PZRESET.

Processor P2 will start executing the BIOS boot code and jump to the physical address 467.

Note that the processor P2 will not start the execution if it is not placed in hold mode by the processor P1 using the PZHOLD bit in the register R1.

Normally, the processor P2 will indicate that it has started execution by setting a semaphor as its first operation. Processor P1 will, after activating bit PZRESET in R1, wait for this semaphor to ensure that processor P2 has started properly (see flag function for bit # 5 above).

Multiprocessor Communication Processors P1 and P2 can communicate using at least two methods. The multiprocessor communication is done by means of a program, and this program can be written in many different ways. Therefore, the description below provides the general guidelines for how this programming can be done.

The first method uses semaphores in shared memory (all memories are shared). Program Instructions TEST_AND_SET was used to perform atomic operations on the semaphores.

This method is preferred when managing common data structures and is normally used by the operating system core. 10 15 20 25 30 35 500 999 17 The second method uses the intermediate processor signal NMI to indicate that a message is available in shared memory.

The handshake method with the intermediate processor signal NMI can be used for each processor communication, but is mainly provided to support distributed interruptions between the two processors. Since the processor P1 will receive all interrupts from the system board controller 2, such as XINTR and XNMI, it must decide which interrupt to process itself and which interrupt to assign to the processor P2. If the processor P1 determines that an interrupt should be assigned to the processor P2, it will first check if the processor P2 is currently running an interrupt manager with a higher priority.

If this is the case, processor P1 will only mark the interrupt as valid for processor P2. If the processor P2 can be interrupted, the processor P1 will write a message indication about which interruption is to be served and interrupt the processor P2 (eg by setting bit no. 6 in the register R2 to "1", or make it possible to set this bit via a buffer circuit), when this bit is read by the processor P2. The P2NMI manager will detect that the processor P2 is working, reads the message and starts the execution of the interrupt service routine. When this is completed, the processor P2 will check if there are any impending interruptions, and if this is the case to serve these interruptions.

Interrupts distributed in this way can support interrupt service routines written for multiprocessor architectures using hardware interrupt distribution. This is done by redirecting all hardware interruptions while allowing the processor P1 to be controlled before the current service routine is called. The processor P1 can then determine which of the processors is to execute the service routine to efficiently emulate the hardware distribution mechanism. 10: of c = ~ c, n VUL] / zU 18 In the above-described embodiment of the invention, only one upgrade processor is shown and discussed. However, it could be possible to provide more than one upgrade processor in a system in accordance with the invention, even if the control of them would be quite complicated. In such a system, only one of the upgrade processors can operate in single processor mode. In multiprocessor mode, however, all the processors in the system could be given a special order of priority, and the system will act as a multiprocessor system with multiple processors. Of course, the bus controller 4 has a register for each of the processors in the system.

Claims (9)

10 15 20 25 30 (f. C 3 CJ \ O \ O CD 19 Patent claim Arrangement in a personal computer device comprising an original, first microprocessor (original processor) and at least one upgrade processor, characterized by a bus controller device (4) for providing two different operating modes for the personal computer device, a single processor mode in which only one overall P1 processor is upgraded. is in operation, so that a software adapted for common computer devices of common type is useful, and a multiprocessor mode for specially adapted software, in which the overall upgrade processor acts as an overall processor and the second processor (P2) or the other processors the processors act as slave processors, the bus controller device (4) being arranged to provide the single processor mode at startup or resetting of the personal computer device, and transfer to multiprocessor mode is controlled by the overall upgrade processor (P1) in response to a program instruction in a computer program in the personal computer device. Arrangement according to claim 1, characterized in that the bus control device device (4) comprises an individual register (R1, R2) for each processor (P1, P2) connectable in the personal computer device, each register serving as a control port for the coupled processor, the registers including various functions needed to perform initialization for the processor or processors in the device to serve as a slave processor or slave processors and communication between the processors. Arrangement according to claim 2, characterized in that the bus control device device comprises a logic control device (LC) comprising a Boolean gate coupling array, which provides logical control of the processors (P1, P2), ragE fl Ien (R1, R2) odïaveaitillsw hmmxmflmazmazmazmazmazmaz 10 is 20 25 30 35 20 Arrangement according to any one of the preceding claims, characterized in that the overall upgrade processor (P1), when the personal computer device is in multiprocessor mode, will respond to a special program instruction for single processor mode, which gives orders to transfer the system from the multiprocessor mode to the single processor mode. Arrangement according to claim 3, characterized in that the registers (R1, R2) are combined control and status registers. Arrangement according to one of Claims 2 to 5, characterized in that the registers (R1 and R2) are located at the same address for the processors (P1 and P2, respectively), and the upgrade processor (P1) always has access to its individual register (R1), and the original processor (P2) always has access to its individual register (R2). Arrangement according to any one of claims 2-3, 5-6, characterized in that in the registers (R1, R2) one of the bits (INTEN), when set, activates interruptions generated using another (IREQ) of the bits which, when an "1" is written into it, generate a pulse which generates an interruption for communication between the processors in the register belonging to another of the processors and which when read indicates the level of an interrupt request signal for this processor. Arrangement according to one of Claims 2 to 3, 5 to 7, wherein only one upgrade processor (P1) is provided, characterized in that a DUAL bit in the register (R2) of the original processor (P2) is "0". , when one processor is installed, and "1" when two processors are installed. a n e - t e c k n a t that a PZHOLD bit in the register (R1) of the overall upgrade processor (P1), when cleared (ie is "0"), allows the original processor (P1) to receive Arrangement according to any one of claims 2-3, 5-8, Û 990 CÉ) r 'Û 21 access to the processor bus, and when it is set (ie is "1") prevents the original processor (P2) from accessing the processor bus.