JP3930116B2 - Computer system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an interrupt control process of a computer system, and more particularly to parallelization of processes in the interrupt control process.
[0002]
[Prior art]
In recent years, various laptop-type or notebook-type personal computers that can be easily carried and operated by a battery have been developed. Interrupt control processing of this personal computer, for example, rapid resume / suspend processing for saving the current operating environment and restoring the operating environment at the next startup of the computer system, and an external device compatible with the docking station and device bay in the computer system The dock / undock process of connecting and disconnecting during the energization of is performed as an interrupt control process during the operation of the operating system (hereinafter referred to as OS).
[0003]
According to the conventional interrupt control processing procedure, when the power microcomputer incorporated in the computer system detects that the power switch is pressed, the power microcomputer issues an interrupt request to the interrupt control logic through the interrupt request line. Alternatively, when the docking station docks the expansion bus connector and the expansion device of the computer system main body to the device bay during the OS operation, each circuit that controls the docking similarly issues an interrupt request to the interrupt control logic.
[0004]
After receiving the interrupt request, the interrupt control logic issues a system management interrupt (hereinafter referred to as SMI) to a central processing unit (hereinafter referred to as CPU).
[0005]
After the CPU receives the SMI signal, the CPU shifts the operation mode to the system management mode (hereinafter referred to as SMM), and activates the interrupt control process stored in the BIOS-ROM. The interrupt control process executes an interrupt control process corresponding to the interrupt signal requested from the CPU.
[0006]
Here, the SMM is a CPU that is set when the CPU shifts to the interrupt control process in the BIOS-ROM when an SMI # signal is input from the computer system to the CPU in a CPU manufactured by Intel Corporation. Is the operation mode.
[0007]
While the CPU is in the SMM, a new interrupt (IRQ, INTR, SMI, etc.) cannot be requested from the computer system to the CPU. Therefore, the interrupt control process must directly execute a series of processes, and when waiting for a predetermined command process issued to various I / O devices is necessary, other processes in the interrupt control process are executed. I couldn't do it, and I had to wait.
[0008]
Next, as an example of the interrupt control process, a rapid suspend process will be described as shown in FIG. The rapid suspend process includes the following five processes.
[0009]
(1) Panel light off sequence processing (S600)
(2) HDD motor off sequence processing (S610)
(3) Register save sequence processing of various I / O devices (S620)
(4) Memory checksum (S630)
(5) Flash ROM rewrite (S640)
Here, in the sequence processes (1) to (3), a certain period of time is required until various I / O devices that have received a command complete the process corresponding to the command. Unless the processing of each sequence is completed, the next sequence cannot be executed.
[0010]
Thus, in the processing of each sequence, the timing of the next sequence processing is delayed by the time required for the command processing of the device. Accordingly, the time for executing the interrupt control process (rapid suspend process) of the system using the SMM is the sum of the times (including the waiting time) corresponding to the commands of each sequence process, and much time is required.
[0011]
Further, in order to accept a power off / on request from the I / O device (power microcomputer) of the computer system during the rapid suspend process, polling is performed for a request from the power microcomputer during the rapid suspend process (S660). I checked it, so I couldn't do it in a timely manner.
[0012]
[Problems to be solved by the invention]
In the prior art described above, when interrupt control processing is executed in the SMM, there is a problem that it takes time for interrupt control processing because other interrupt requests cannot be accepted.
[0013]
Further, since interrupt requests from other I / O devices cannot be accepted during the interrupt control process, a special process for polling various I / O devices to check for requests is required.
[0014]
Accordingly, the present invention has been made to solve the above-described problem, and by enabling the CPU operation mode to be interrupted by an SMM that does not accept an interrupt request, and by parallelizing necessary processing during interrupt control processing. The object is to provide a reduction in the processing time of the entire interrupt control process.
[0015]
[Means for Solving the Problems]
According to the present invention, in a computer system that executes predetermined processing in a system management mode that does not accept an interrupt request, means for generating a system management interrupt request during operation of the OS, and responding to the first system management interrupt request Means for changing the CPU operation mode to the system management mode, and after the CPU operation mode is changed to the system management mode, the CPU operation mode can accept an interrupt request that can accept an interrupt request. Means for setting the mode, and means for executing the plurality of processes in parallel by using a plurality of tables for individually managing the operations of the plurality of processes constituting the interrupt control process in the interrupt acceptance mode. Equipped with The means for setting the operation mode of the CPU to the interrupt acceptable mode comprises means for storing CPU state map information in the second area of the memory in response to a second system management interrupt request. The means for setting the operation mode of the CPU to the interrupt acceptable mode further includes the CPU state map information stored in the first area of the memory and the CPU stored in the second area. Means to replace state map information It is characterized by that.
[0016]
According to such a configuration, when the system is initialized, the CPU state map information is stored in the memory so that when the system management interrupt request is received during the OS startup, the CPU operation mode is interrupted from the system management mode. By changing to a possible mode and executing the interrupt control process in an interruptible mode, the necessary processes in the interrupt control process can be parallelized, and the processing time of the entire interrupt control process can be reduced. .
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 shows the configuration of a computer system according to an embodiment of the present invention. This computer system is a notebook type or laptop type portable computer that can be driven by a battery, and a processor bus 1, an internal PCI bus 2, an internal ISA bus 3, and an I2C bus 4 are arranged on the system board. Is done. 2 is connected to the docking connector 10 provided in the portable computer main body as an expansion unit for function expansion as required by the user. The docking connector 10 includes three connector elements 101, 102, and 103 as shown in the figure.
[0018]
In the computer main body, CPU 11, host-PCI bridge device 12, memory 13, display controller 14, DSP interface gate array (hereinafter referred to as DSP IF GA) 15, internal PCI-ISA bridge device 16, device bay controller 17, PCI -DS (DS: docking station) bridge device 18, BIOS-ROM 19, hard disk drive 20, keyboard controller 21, real-time clock (hereinafter referred to as RTC) 22, I / O control gate array 23, power supply controller (hereinafter referred to as PSC) 24) and the like are provided.
[0019]
The docking station 30 is used for expansion of expansion devices such as a PCI expansion card, an ISA expansion card, a PC card, a hard disk drive, and a CD-ROM drive. As shown, an external PCI bus 5 and an external ISA bus 6 are provided as expansion buses, to which a PCI expansion slot, an ISA expansion slot, and the like are connected. Here, the hard disk drive 36 is connected to the external ISA bus 6.
[0020]
In the docking station 30, a DS-PCI / ISA bridge device 31, a DS controller 33, an EEPROM 34, and the like are also provided.
Next, the function and configuration of each component provided in the computer main body of FIG. 1 will be described.
[0021]
The CPU 11 is realized by, for example, a microprocessor “pentium” manufactured and sold by Intel Corporation. The processor bus 1 directly connected to the input / output pins of the CPU 11 has a 64-bit data bus.
[0022]
The host-PCI bridge device 12 is a bridge LSI that connects the processor bus 1 and the internal PCI bus 2, and functions as one of the bus masters of the PCI bus 2. The host-PCI bridge device 12 has a function of bidirectionally converting a bus cycle including data and an address between the processor bus 1 and the internal PCI bus 2 and a function of controlling access to the memory 13 via the memory bus. Etc.
[0023]
Further, the host-PCI bridge device 12 includes an interrupt control circuit that issues an interrupt to the CPU 11, and this circuit includes an SMI generation circuit 121, an SMI factor register 122, a soft SMI timer enable register 123, and a counter register 124. The
[0024]
The SMI generation circuit 121 issues an SMI # signal to the SMI # pin of the CPU 11 in response to an on / off operation of the power switch, a dock / undock operation of the docking station, and an H / W interrupt from the hot key.
[0025]
The SMI factor register 122 is connected to the SMI generation circuit 121 and is a register for identifying the factor of the SMI generation. Here, the power switch ON / OFF operation, the docking station dock / undock operation, the hot key Stores a status bit indicating the state of the H / W interrupt.
[0026]
The soft SMI timer enable register 123 is a register that enables the counter register 1123 to start down-counting.
The counter register 124 is set to a value obtained by subtracting the current time from the earliest next activation time in each sequence table to be described later. When the counter value reaches “0”, the SMI # signal is sent to the CPU 11. Is issued.
[0027]
The memory 13 is a memory device that stores an operating system, a device driver, an application program to be executed, processing data, and the like, and includes a plurality of DRAM modules.
[0028]
The memory 13 includes a system memory 131 mounted in advance on the system board and an SM-RAM 132 used as a part of the system memory.
[0029]
As the DRAM modules constituting the system memory 131 and the SM-RAM 132, a high-speed memory that needs to supply a memory clock for each bank, such as a synchronous DRAM or a Rambus, is used.
[0030]
The SM-RAM 132 is composed of a non-volatile memory or a backed up 64-kbyte memory, and is provided with areas A and B for storing a CPU state map, which will be described later, and a sequence table for parallelizing interrupt control processing. It is done.
[0031]
Further, the SM-RAM 132 stores password information input by the user when starting the system and an SMI handler for designating a jump destination to the SM-BIOS 19 when starting SMM.
[0032]
The memory 13 is connected to the host-PCI bridge device 12 via a dedicated memory bus having a 32-bit or 64-bit data bus. The data bus of the processor bus 1 can be used as the data bus of the memory bus. In this case, the memory bus includes an address bus and various memory control signal lines.
[0033]
The internal PCI bus 2 is a clock synchronous type input / output bus, and all cycles on the internal PCI bus 2 are performed in synchronization with the PCI bus clock. The frequency of the PCI bus clock is a maximum of 33 MHz. The PCI bus 2 has an address / data bus used in a time division manner. This address / data bus is 32 bits wide.
[0034]
A data transfer cycle on the PCI bus 2 includes an address phase and one or more data phases following the address phase. In the address phase, the address and transfer type are output, and in the data phase, 8-bit, 16-bit, 24-bit or 32-bit data is output.
[0035]
The display controller 14 is one of the bus masters of the PCI bus 2 similarly to the host-PCI bridge device 12, and displays the image data of the video memory (VRAM) 143 on the LCD 141 or an external CRT display 142.
[0036]
The DSP interface gate array 15 is one of PCI devices, and constitutes a DSP system for performing various sound processing and telephone / data communication processing in cooperation with the DSP 151, the modem (CODEC) 152, and the sound CODEC 153.
[0037]
The DSP interface gate array 15 communicates with the DSP 151, MODEM (CODEC) 152, and sound CODEC 153 under the control of a dedicated device driver program that is read and executed in the memory 13, and performs the digital signal processing function of the DSP 151. Controls sound processing and communication processing used.
[0038]
The internal PCI-ISA bridge device 16 is a bridge LSI that connects the internal PCI bus 2 and the internal ISA bus 3 and functions as one of PCI devices. The internal PCI-ISA bridge device 16 includes a PCI bus arbiter and a DMA controller. A BIOS-ROM 19, HDD 20, keyboard controller 21, RTC 22, and I / O control gate array 23 are connected to the internal ISA bus 3.
[0039]
The device bay controller 17 is one of PCI devices, and controls an external expansion device with a device bay specification that is docked.
The PCI-DS bridge device 18 controls connection and disconnection of the bus with the docking station 30. That is, the PCI-DS bridge device 18 is a bridge LSI that connects the internal PCI bus 2 and a docking bus corresponding to the PCI bus, and functions as one PCI device. The docking bus 7 is led out to the outside via the connector element 101 of the docking connector 10 and connected to the docking station 30.
[0040]
The BIOS-ROM 19 is for storing a system BIOS (Basic I / O System), and is configured by a flash memory (EEPROM) so that the program can be rewritten. The system BIOS includes an IRT routine (POST) executed at the time of system boot, a device driver (runtime) for controlling various I / O devices, and a system management program (SM-BIOS) for executing interrupt control processing. And password information set by the setup routine and the user.
[0041]
The system management program is an interrupt program executed in the SMM, and includes various SMI service routines such as an SMI handler and a hot key processing routine. The SMI handler is for starting an SMI service routine according to the SMI generation factor. When an SMI due to a hot key occurs, the hot key processing routine is started, and when an SMI due to another factor occurs. The SMI service routine corresponding to the factor is started. In the embodiment of the present invention, the SM-BIOS issues an SMI # signal to the CPU 11 by an I / O trap instruction and a soft SMI timer, and executes an interrupt control process from the SMI service routine.
[0042]
A hard disk drive (HDD) 20 is a primary HDD that is connected to the internal ISA bus 3 and stores an operating system (hereinafter referred to as OS). The hard disk drive 20 is in an access lock state by an access lock mechanism. Further, the hard disk drive 20 includes a hard disk controller that controls input / output with the system, a memory that stores a password, and a medium that can store data of the computer system.
[0043]
The I / O control gate array 23 is a bridge LSI that connects the internal ISA bus 3 and the I2C bus 4 and includes a plurality of register groups that can be read / written by the CPU 11. By using these register groups, the CPU 11 can communicate with the power supply controller 24 and the DS controller 33 on the I2C bus 4.
[0044]
A plurality of control signal lines connected to the docking station 30 are led out from the I / O control gate array 23 via the connector element 102 of the docking connector 10. The I / O control gate array 23 detects docking / undocking between the computer main body and the docking station 30, and further activates when the docking station 30 is connected while the computer main body is powered on. Control is performed so that the expansion unit in the docking station 30 is not destroyed or the system malfunctions due to wire insertion / extraction.
[0045]
Further, the I / O control gate array 23 incorporates an interrupt register 231, and data indicating ON / OFF of the power switch is transmitted via the power controller 24 and data indicating docking / undock in the docking station 30 is transmitted via the DS controller 33. Is set.
[0046]
The I2C bus 4 is a bidirectional bus composed of one clock signal line and one data line (SDA), which is led out via the connector element 103 of the docking connector 10.
[0047]
The power controller 24 is for powering on / off the computer body in accordance with on / off of a power switch, and also performs power control according to docking / undocking with the docking station 30.
[0048]
Next, components of the docking station 30 of FIG. 2 will be described.
As described above, the docking station 30 is an expansion unit that can be detachably attached to the portable computer main body. FIG. 3 shows how the computer main body is mounted on the docking station 30.
[0049]
The DS-PCI / ISA bridge device 31 provided in the docking station 30 having such an external appearance connects the docking bus 7 led out from the computer main body to the docking station 30, the external PCI bus 5 and the external ISA bus 6. It is a bridge LSI. The DS-PCI / ISA bridge device 31 is one of PCI devices.
[0050]
The DS controller 33 is a microcomputer for controlling on / off of the power supply of the docking station 30 and docking / undocking of the portable computer main body and the docking station 30. Communicates with the O control gate array 23.
[0051]
The EEPROM 34 stores PnP information necessary for plug and play, such as attributes (address, DMA channel, IRQ number, etc.) of the expansion card installed in the expansion slot of the docking station 30. The This PnP information is transmitted via the I2C bus 4 under the control of the system BIOS of the BIOS-ROM 19 when the computer main body and the docking station 30 are docked or when the computer main body or the docking station 30 is powered on. Read from EEPROM 34 by / O control gate array 23.
[0052]
The card controller 35 controls a PC card conforming to the PCMCIA / card bus similarly to the card controller 17 in the computer main body.
Next, referring to the flowcharts in FIGS. 4 and 5 and the CPU memory map in FIG. 6, the operation of the computer system in FIG. 1 when the power is turned on (during initialization processing) will be described.
[0053]
When the computer system of FIG. 1 is powered on, the CPU 11 is reset and starts operating in the real mode (S210). At system power-on, the system BIOS in the BIOS-ROM 19 is assigned to the CPU memory addresses F0000 to FFFFF, and the CPU 11 fetches the instruction at the address FFFF0. As a result, the execution of the POST (Power On Self Test) routine of the system BIOS is started in the real mode environment.
[0054]
The POST routine changes the operation mode of the CPU 11 to the real mode by setting the MSW register of the CPU 11 (S220). Thereafter, in the protect mode, initialization processing of various gate arrays of the computer system and read / write compare check of the system memory 131 / SM-RAM 132 are executed (S230 to 240).
[0055]
Next, as shown in FIG. 6, the SM-RAM 132 is allocated to 30000H by the SM-BASE register at the start of initialization of the POST routine, and the SM-BIOS when the SMI # signal is issued to the CPU 11. In order to set the far jump destination, the far jump destination is set in the SMI handler assigned to 38000H (S250).
[0056]
The POST routine enables the SMI generation circuit 121 to change the allocation of the CPU memory map of the SM-RAM 132 after the SMI # signal is issued to the CPU 11 so that the SMI generation circuit can issue the SMI # signal to the CPU 11. (S310).
[0057]
The POST routine sets a BIOS function call in the AH register of the CPU, sets an interrupt trap with a specific I / O address, and issues an SMI # signal (hereinafter referred to as an I / O trap SMI) to the CPU 11 ( S320).
[0058]
As the SMI # signal is issued to the CPU 11, the CPU state map at the time of the occurrence of the interrupt is automatically stored in 512 Kbytes after 3FE00H, and the SMI handler is called. The SMI handler activates the far jump destination SM-BIOS set in the SMI handler, and changes the allocation of the CPU memory map of the SM-RAM 132.
[0059]
Here, the CPU state map is to issue an SMI # signal to the CPU 11 and when the operation mode of the CPU 11 is shifted to SMM, the current state of the CPU at the time of issuing the SMI # signal is displayed in a predetermined area in the SM-RAM 132. The information stored in the area is used to store the information in the CPU 11 when the information is stored and exited from the SMM.
[0060]
The SM-BIOS rewrites the SM-BASE register value to FFFE0000H (S330). The CPU memory map of the SM-RAM 132 set by rewriting the SM-BASE register value is allocated to 64K bytes after FFFE0000H as shown in FIG.
[0061]
The SM-BIOS executes the RSM instruction after rewriting the value of the SM-BASE register, and prohibits subsequent generation of the SMI # signal (S340 to S350).
The POST routine that has returned from the SM-BASE register value rewrite interrupt process creates a unique mode that can be interrupted by the CPU 11, and the CPU state map stored in 512 Kbytes after 3FE00H is 512 bytes after FFFEFE00H in SM-RAM132. Write to area B (S270).
[0062]
Here, the unique mode in which the CPU 11 can be interrupted is a state in which all interrupts (IRQ, NMI, etc.) including the SMI are possible, and the interrupt can be managed by the system BIOS.
[0063]
Next, the POST routine executes the enabling of the SMI generation circuit 121 to initialize the various devices (default values for the various devices) so that the SMI generation circuit can issue the SMI # signal to the CPU 11 after the OS is started. Setting) is executed (S280 to S290).
[0064]
After completion of the default value setting process for various devices, the POST routine changes the operation mode of the CPU 11 from the protected mode to the real mode by setting the MSW register of the CPU 11 and activates the OS (S300).
[0065]
Next, the operation of the interrupt control process during OS startup will be described with reference to the flowchart of FIG.
After completion of the POST routine of the system BIOS, control is transferred to the OS, and then a suspend / resume request or a desk station docking / undocking request is generated, that is, an interrupt register 231 in the I / O control gate array 23. When the power switch is turned on / off or the dock / undock state change of the docking station 30 is set, the SMI generation circuit 121 is requested to issue an SMI # signal via the point-to-point interrupt line. The SMI generation circuit 121 sets a factor bit corresponding to the SMI factor register 122 and issues an SMI # signal to the CPU 11.
[0066]
When the CPU 11 receives the SMI # signal, the operation mode of the CPU 11 is changed to SMM, and the CPU state at the time of interruption is stored in the area B in the SM-RAM (S410).
[0067]
Next, the far jump destination SM-BIOS set in the SMI handler in the SM-RAM is activated, and the SM-BIOS checks the SMI occurrence factor. The SM-BIOS checks the contents of the SMI factor register 122. If it is determined that the SM-BIOS is in a state change accompanying the on / off operation of the power switch, the CPU stored in the area B of the SM-RAM 132 The state map information is exchanged with the CPU state map information of the area A stored at the time of initialization (S420 to S430).
[0068]
In order to switch the operation mode of the CPU 11 to the original mode and perform rapid suspend processing in parallel, the SM-BIOS performs rapid suspend processing on the value of the program counter (hereinafter referred to as PC) in the CPU state map information set at initialization. Is set to the BIOS-ROM address in which is stored, and the RSM instruction is executed. In response to the RSM command, the CPU 11 restores the CPU state map information stored in the area B in the SM-RAM 132 to each register in the CPU 11 (S440).
[0069]
After the CPU 11 changes to the unique mode, the next instruction is executed from the address value set in the PC of the CPU 11, and the rapid suspend process described later is executed in parallel as shown in FIG. 8 (S450).
[0070]
After completing the parallel execution of the rapid suspend process, the system BIOS issues an I / O trap SMI to the CPU 11. The system BIOS sets a BIOS function in the SMM mode in the AH register of the CPU 11 before issuing the SMI # signal (S460).
[0071]
After the CPU 11 transitions to the SMM mode, SM-BIOS is activated. The SM-BIOS checks the SMI factor register 122 to confirm the cause of the SMI occurrence. After confirming that the SMI is issued by the I / O trap SMI, the SM-BIOS confirms the value of the AH register of the area B in which the CPU state map information is stored. The SM-BIOS The CPU state map information stored in the area B in the SM-RAM 132 is mutually replaced with the contents of the area A (S470).
[0072]
After executing the RSM instruction, the SM-BIOS restores the CPU state map information stored in the area B in the SM-RAM 132 to the CPU 11 and ends all the interrupt control processes related to the rapid suspend process (S480).
[0073]
Next, the operation of parallel processing using interrupts will be described with reference to the progress timing of CPU processing in FIG. 8, each working area information in the sequence table in FIG. 9, and the flowchart of each sequence processing in FIG. .
[0074]
The system BIOS sets a BIOS function in the AH register of the CPU 11 and issues an I / O trap SMI to the CPU 11 in order to start the panel off sequence process of the rapid suspend process (S500).
[0075]
After the operation mode of the CPU 11 transitions to SMM, the panel off sequence process is called. In the panel off sequence process, first, a busy check of the power supply controller 24 is requested (S510). Since the busy check of the power supply controller 24 spends a predetermined interval (waiting time), the panel off sequence processing is executed in the sequence table 125 in the SM-RAM 132 after the busy check request of the power supply controller 24, and the current program counter value “A”, A flag indicating that the panel off sequence process is in operation and an interval timer value (next activation time: interval 1) are set (S520).
[0076]
In the panel off sequence processing, the value of the next activation time in each sequence table 125 is read, the sequence of the earliest activation time is determined, and the value obtained by subtracting the earliest activation time selected from the current time is set in the counter register 124. (S530 to S550). In this case, since only the operation flag of the panel off sequence process is set, the earliest next activation time is the activation time of the panel off sequence.
[0077]
After the next activation time is set in the counter register 124, the panel off sequence process sets the SMI timer enable register 123 and starts the count down of the counter register 124 (S560).
[0078]
In the panel off sequence process, the RSM instruction is executed, and the process returns to the main routine of the rapid suspend process (S570).
After returning to the main routine of the rapid suspend process, the rapid suspend process sets the SM-BIOS function in the AH register of the CPU 11, issues an I / O trap SMI to the CPU 11, and starts the HDD motor off sequence process (S500). ).
[0079]
In the activated HDD motor off sequence process, first, a busy check of the hard disk controller built in the HDD 20 is requested (S510). Since the busy check of the hard disk controller spends a predetermined interval (waiting time), the HDD motor off sequence processing, after requesting the busy check of the hard disk controller, the current program counter value “B” in the sequence table 125 in the SM-RAM 132, the hard disk A flag indicating that the controller off sequence process is in operation and an interval timer value (next activation time: interval 1) are set (S520).
[0080]
The hard disk controller off-sequence processing reads the next start time value in each sequence table, determines the earliest start time sequence, and sets the value obtained by subtracting the earliest start time selected from the current time in the counter register 124 (S530 to S550). In this case, since the next activation time of the panel off sequence process is earlier than the next activation time of the HDD motor off sequence process, the earliest next activation time is the activation time of the panel off sequence.
[0081]
In the HDD motor off sequence processing, after setting the next activation time of the panel off sequence in the counter register 124, the SMI timer enable register 123 is set, and the count down of the counter register 125 is started (S560).
[0082]
The HDD motor off sequence process executes the RSM command and returns to the main routine of the rapid suspend process (S570).
After returning to the main routine of the rapid suspend process, the rapid suspend process sets an SM-BIOS function in the AH register of the CPU 11 and then issues an I / O trap SMI to the CPU 11 to perform a save sequence process for various I / O registers. Start (S500).
[0083]
In the save sequence processing of various I / O registers, a command is issued to request the output of data stored in various I / O registers (S510). Since processing of data output requests of various I / O registers spends a predetermined interval (waiting time), the storage sequence processing of various I / O registers is output to the current program counter in the sequence table 125 in the SM-RAM 132 after command output. A value “C”, a flag indicating that the save sequence processing of various I / O registers is in operation, and an interval timer value (next activation time: interval 1) are set (S520).
[0084]
The save sequence processing of various I / O registers reads the next start time value in each sequence table 125, determines the earliest start time sequence, and subtracts the earliest start time selected from the current time. The counter register 124 is set (S530 to S550). In this case, the next startup time of the panel off sequence process is earlier than the next startup time of the HDD motor off sequence process and the next startup time of the storage sequence process of various I / O registers. This is the off-sequence startup time.
[0085]
In the save sequence processing of various I / O registers, after setting the next activation time of the panel off sequence in the counter register 124, the SMI timer enable register 123 is set, and the counter register 124 starts to count down (S560).
[0086]
The save sequence processing of various I / O registers executes the RSM instruction and returns to the main routine of rapid suspend processing (S570).
In this case, since the startup time of the panel off sequence process has already passed, the counter register 124 reaches zero count immediately after the save sequence process of various I / O registers is executed. In response to reaching the zero count of the counter register 124, an I / O trap SMI is issued to the CPU 11. The SM-BIOS executes the panel off sequence process which is the earliest start-up time from each sequence table in the SM-RAM 132 (S500).
[0087]
In the panel off sequence process, first, after a busy check of the power supply controller 24, a panel off command is output to the power supply controller 24 (S510). Since the power supply controller 24 spends a predetermined interval (waiting time) to execute the processing of the panel off command, the panel off sequence processing is output to the sequence table 125 in the SM-RAM 132 after the panel off command is output to the power supply controller 24. A program counter value “A2”, a flag indicating that the panel off sequence process is in operation, and an interval timer value (next activation time: interval 2) are set (S520).
[0088]
In the panel off sequence processing, the value of the next activation time in each sequence table 125 is read, the sequence of the earliest activation time is determined, and the value obtained by subtracting the earliest activation time selected from the current time is set in the counter register 124. (S530 to S550). In this case, operation flags for the panel off sequence processing, the HDD motor off sequence processing, and the storage sequence processing of various I / O registers are set. The earliest next startup time is the startup time of the HDD motor off sequence.
[0089]
After the next activation time is set in the counter register 124, the panel off sequence process sets the SMI timer enable register 123 and starts the count down of the counter register 124 (S560).
[0090]
In the panel off sequence process, the RSM instruction is executed, and the process returns to the main routine of the rapid suspend process (S570).
Since the startup time of the HDD motor off sequence process has already passed, the counter register 124 becomes zero count immediately after the panel off sequence process executes the RSM instruction. In response to reaching the zero count of the counter register 124, an I / O trap SMI is issued to the CPU 11. The SM-BIOS executes the HDD motor-off process that is the earliest start-up time from each sequence table in the SM-RAM 132 (S500).
[0091]
The HDD motor off sequence process outputs a hard disk controller motor off command to the hard disk controller after the busy check of the hard disk controller (S510). Since the hard disk controller spends a predetermined interval (waiting time) to execute the motor off command processing, the HDD motor off sequence processing outputs the motor off command to the hard disk controller and then stores the current program in the sequence table 125 in the SM-RAM 132. A counter value “B2”, a flag indicating that the HDD motor off sequence processing is in operation, and an interval timer value (next activation time: interval 2) are set (S520).
[0092]
The HDD motor off sequence process reads the value of the next start time in each sequence table 125, determines the earliest start time sequence, and stores the value obtained by subtracting the earliest start time selected from the current time in the counter register 124. Set (S530 to S550). In this case, the operation flags of the panel off sequence process, the HDD motor off sequence process, and the save sequence process of various I / O registers are set. The earliest next activation time is the activation time of the save sequence of various I / O registers.
[0093]
After the next activation time is set in the counter register 124, the panel off sequence process sets the SMI timer enable register 123 and starts the count down of the counter register 124 (S560).
[0094]
In the panel off sequence process, the RSM instruction is executed, and the process returns to the main routine of the rapid suspend process (S570).
Since the start time of the storage sequence processing of various I / O registers has already passed, the counter register 124 becomes zero count immediately after the HDD motor off sequence processing executes the RSM instruction. In response to reaching the zero count of the counter register 124, an I / O trap SMI is issued to the CPU 11. The SM-BIOS executes the storage sequence processing of various I / O registers that is the earliest start-up time from each sequence table in the SM-RAM 132 (S500).
[0095]
In the save sequence processing of various I / O registers, a ready signal is received from various I / Os in response to a command output of a register data request. The save sequence processing of various I / O registers reads register data in the various I / Os and saves the data in a predetermined backed up area in the system memory (S510). In the save sequence processing for various I / O registers, a flag indicating that the save sequence processing for various I / O registers is completed is set in the sequence table 125 in the SM-RAM 132 (S520).
[0096]
The save sequence processing of various I / O registers reads the value of the next activation time in each sequence table, judges the sequence of the earliest activation time, and counts the value obtained by subtracting the earliest activation time selected from the current time It is set in the register 124 (S530 to S550). In this case, operation flags for the panel off sequence process and the HDD motor off sequence process are set. The earliest next startup time is the startup time of the HDD motor off sequence.
[0097]
In the save sequence processing of various I / O registers, after setting the next activation time in the counter register 124, the soft SMI timer enable register 123 is set, and the counter register 124 starts to count down (S560).
[0098]
The save sequence processing of various I / O registers executes the RSM instruction and returns to the main routine of rapid suspend processing (S570).
Since the startup time of the HDD motor off sequence processing has already passed, the counter register 124 reaches zero count immediately after the storage sequence processing of various I / O registers is executed. In response to reaching the zero count of the counter register 124, an I / O trap SMI is issued to the CPU 11. The activated SM-BIOS executes the panel off sequence process which is the earliest activation time from each sequence table 125 in the SM-RAM 132 (S500).
[0099]
In the panel off sequence process, a ready signal is received from the power supply controller 24 in response to the panel off command output. In the panel off sequence process, a 220 ms wait process is executed after the ready signal is received (S510). In the panel off sequence processing, the current program counter value “A3” in the sequence table 125 in the SM-RAM 132, a flag indicating that the panel off off sequence processing is in operation, and an interval timer value (next activation time: interval 3) Is set (S520).
In the panel off sequence processing, the value of the next activation time in each sequence table 125 is read, the sequence of the earliest activation time is determined, and the value obtained by subtracting the earliest activation time selected from the current time is set in the counter register 124. (S530 to S550). In this case, operation flags for the panel off sequence process and the HDD motor off sequence process are set. The earliest next startup time is the startup time of the HDD motor off sequence.
[0100]
In the panel off sequence process, after setting the next activation time in the counter register 124, the soft SMI timer enable register 123 is set, and the counter register 124 starts to count down (S560).
[0101]
In the panel off sequence process, the RSM instruction is executed, and the process returns to the main routine of the rapid suspend process (S570).
Since the startup time of the HDD motor off sequence process has already passed, the counter register 124 becomes zero count immediately after the panel off sequence process executes the RSM instruction. In response to reaching the zero count of the counter register 124, an I / O trap SMI is issued to the CPU 11. The activated SM-BIOS executes the HDD motor off sequence process that is the earliest activation time from each sequence table 125 in the SM-RAM 132 (S500).
[0102]
In the HDD motor off sequence process, a ready signal is received from the hard disk controller in response to the hard disk controller off command output (S510). In the HDD motor off-sequence process, a flag indicating that the HDD motor off-off sequence process is completed is set (S520).
The HDD motor off sequence process reads the value of the next start time in each sequence table 125, determines the earliest start time sequence, and stores the value obtained by subtracting the earliest start time selected from the current time in the counter register 124. Set (S530 to S550). In this case, only the operation flag of the panel off sequence process is set. The earliest next activation time is the activation time of the panel off sequence.
[0103]
In the HDD motor off sequence processing, after setting the next activation time in the counter register 124, the soft SMI timer enable register 123 is set, and the counter register 124 starts to count down (S560).
[0104]
In the panel off sequence process, the RSM instruction is executed, and the process returns to the main routine of the rapid suspend process (S570).
The main routine of the rapid suspend process executes a checksum of the memory 13 and stores the result in a predetermined area of the memory. Next, the main routine of the rapid suspend process stores password information and PnP information in the BIOS-ROM 19. If the count of the counter register 124 reaches zero during rewriting of the BIOS-ROM 19, an I / O trap SMI is issued to the CPU 11 (S500). The rewriting process of the BIOS-ROM 19 is temporarily interrupted, and the status map information of the CPU 11 is stored in the area B in the SM-RAM. Based on the function set in the AH register of the CPU, SM-BIOS processing is started.
[0105]
The activated SM-BIOS confirms the contents of the SMI factor register 122 and the like, and executes a panel off sequence process. In the panel off sequence process, after a wait of 220 ms, the LCD panel is disabled, and a flag indicating that the panel off / off sequence process is completed is set (S510 to S520).
In the panel off sequence processing, since all the operating flags in each sequence table 125 have been completed, nothing is set in the counter register 124, the RSM instruction is executed, and the area B in the SM-RAM 132 is set. The stored CPU state map information is restored to the CPU, and the process returns to the main routine of the rapid suspend process (S530 to S570).
[0106]
The rewriting process of the BIOS-ROM 19 is continued from the interrupted location, and the process ends. Furthermore, the main part of the rapid suspend process is to check the operation flag in the SM-RAM 132 whether all the sequence processes have been completed, and after confirming that all the sequence processes have been completed, parallel processing using interrupts End (rapid suspend process).
[0107]
According to the configuration of the present embodiment, since the response from the I / O device can be received by the interrupt control process after the CPU 11 is switched to the unique mode, the detection can be performed more reliably than the polling process.
[0108]
For example, even if the power switch is pressed during OS startup and the power switch is pressed again during the rapid suspend process, the power controller 24 turns on the power switch in the interrupt register in the I / O controller GA23. / Set the off state. Since the interrupt register 231 is connected to the SMI 121 generation circuit 121 via a point-to-point interrupt line, the SMI # signal is issued to the CPU 11 by setting a bit corresponding to the state change in the interrupt register 231. I can do it.
[0109]
In the embodiment of the present invention, the parallel operation of the rapid suspend process has been described. However, the normal suspend / resume process and the dock / undock process can also be performed by switching the CPU to the original mode.
[0110]
【The invention's effect】
As described above, according to the present invention, the SMM that does not accept an interrupt request enables the CPU operation mode to be interrupted, and the processing time required for the entire interrupt control process is obtained by parallelizing necessary processes during the interrupt control process. Can be shortened.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a system configuration of a computer system according to an embodiment of the present invention.
FIG. 2 is an exemplary block diagram showing the configuration of a docking station used in the system according to the embodiment;
FIG. 3 is an exemplary view showing a state in which the computer main body according to the embodiment is mounted on a docking station.
FIG. 4 is an exemplary flowchart illustrating an operation procedure when power is turned on (initialization processing) in the system according to the embodiment;
FIG. 5 is an exemplary flowchart illustrating an operation procedure of an SM-BASE register value rewrite process in the system according to the embodiment;
FIG. 6 is an exemplary block diagram showing a memory map of the CPU in the system according to the embodiment;
FIG. 7 is an exemplary flowchart illustrating a procedure of interrupt control processing during OS activation in the system according to the embodiment;
FIG. 8 is a timing chart showing a CPU progress state of rapid suspend processing parallelized in the system of the embodiment;
FIG. 9 is an exemplary block diagram showing the configuration of a sequence table provided in the SM-RAM in the system according to the embodiment;
FIG. 10 is an exemplary flowchart illustrating the sequence of each sequence process during the rapid suspend process in the system according to the embodiment;
FIG. 11 is a flowchart illustrating a procedure of a conventional interrupt control process during OS startup.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Processor bus, 2 ... Internal PCI bus, 3 ... Internal ISA bus, 4 ... I2C bus, 5 ... External PCI bus, 6 ... External ISA bus, 10 ... Docking connector, 11 ... CPU, 12 ... Host-PCI bridge apparatus , 13 ... Memory, 14 ... Display controller, 15 ... DSP interface gate array, 16 ... Internal PCI-ISA bridge device, 17 ... Device bay controller, 18 ... PCI-DS bridge device, 19 ... BIOS-ROM, 20 ... HDD, 21 ... Keyboard controller, 22 ... RTC, 23 ... I / O control gate array, 24 ... Power supply controller (PSC), 30 ... Docking station, 31 ... DS-PCI / ISA bridge device, 33 ... DS controller, 35 ... Card controller 36 ... HDD, 00 ... computer, 131 ... system memory, 132 ... SM-RAM

Claims (4)

In a computer system that executes a predetermined process in a system management mode that does not accept an interrupt request,
Means for generating a system management interrupt request during operation of the OS;
Means for changing a CPU operation mode to the system management mode in response to a first system management interrupt request;
Means for setting the operation mode of the CPU to an interrupt acceptable mode capable of accepting an interrupt request after the operation mode of the CPU is changed to the system management mode;
Means for executing the plurality of processes in parallel by using a plurality of tables for individually managing the operations of the plurality of processes constituting the interrupt control process in the interrupt acceptance mode ,
The means for setting the operation mode of the CPU to the interrupt acceptable mode comprises means for saving CPU state map information in the second area of the memory in response to a second system management interrupt request.
The means for setting the operation mode of the CPU to the interrupt acceptance mode further includes the CPU state map information stored in the first area of the memory and the CPU state stored in the second area. A computer system comprising means for replacing map information . The means for setting the operation mode of the CPU to the interrupt acceptable mode executes a return (RSM) instruction when the CPU operation mode is set to the system management mode, and the second mode in the memory the computer system of claim 1, wherein the CPU state map information stored in the area characterized by comprising means for setting said CPU. The computer system, after completing the interrupt control process in the interrupt acceptance mode, means for generating a system management interrupt request again to change the operation mode of the CPU to the system management mode, and the system management Means for storing CPU state map information in the second area of the memory in response to an interrupt request; and the CPU state map information stored in the first area of the memory and the second area. 3. The computer system according to claim 2 , further comprising means for replacing the CPU state map information stored in the area. When the computer system returns from the system management mode to the CPU mode before the system management interrupt request is generated, the CPU state map information stored in the second area in the memory is transferred to the CPU. 4. The computer system according to claim 3 , further comprising means for setting.

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