JP2782367B2 - Digital computing system with low power mode - Google Patents

Description

The present invention generally relates to digital computing systems having a low power mode. More particularly, the present invention relates to a digital computing system that prepares for entering a low power mode by signaling status information regarding conditions for exiting the low power mode.

2. Description of the Related Art Digital computing systems, especially integrated circuit computing systems, generally have the ability to switch to a low power mode during periods of inactivity, so that various subsystems are shut down to reduce power consumption. Is done. Typically, upon the occurrence of a predetermined external event, the system is "woken up" from the low power mode to return to normal processing.

U.S. Patent No. 4,75, both assigned to the assignee of the present invention.
Nos. 8,559 and 4,758,945 disclose examples of digital computing systems that respond to specific software instructions by switching to one of two available low power modes. The system described here is an MC1468 from Motorola of Austin, Texas, USA
Available as an integrated circuit designated 05. Any of the two available low power modes disclosed can be terminated by a reset or interrupt event. In the event of an interrupt event, the mask bit that prevents certain interrupts from being recognized by the system must be cleared in order for the maskable interrupt event to exit the low power mode.

The above-mentioned patents describe systems suitable for conventional "hand-built" integrated circuit design methodologies. However, as integrated circuit computing systems transition toward a "modular" design methodology to allow for faster design of custom systems, some reset and interrupt control circuits may be implemented in the logic of the central processing unit. And may be removed from physical proximity. In this case, it is necessary to change a conventionally known technique in order to end the low power mode.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an improved digital computing system having a low power mode, wherein the termination condition of this low power mode before switching to the low power mode. The information about is communicated.

These and other objects of the present invention are achieved by a digital computing system that executes software instructions in synchronization with a clock signal, and an apparatus for switching to a state of low energy consumption comprises: Any of multiple events,
Storage means for storing information determining whether the system should have the ability to terminate the low energy consumption state; instructions for decoding one of the predetermined software instructions and in response to generating a control signal; A decoding means, and a bus control means coupled to the instruction decoding means and the communication bus for receiving a control signal from the instruction decoding means and placing a predetermined signal having information stored in the storage means on the communication bus. Have.

These and other objects and advantages of the present invention will become apparent to those skilled in the art from the following detailed description, taken in conjunction with the drawings.

Embodiments The terms “positive”, “positive”, “deny” and “negative” deal with mixed signals of “active H” and “active L” If used to avoid confusion. "agree with"
And "positive" is used to indicate that the signal is active or logically true. "Deny" and "deny" are used to indicate inactive, ie, logically false. Further, the terms "set" and "clear" are used to refer to a status bit or similar device as being in a logically true or logically false state, respectively.

FIG. 1 illustrates an integrated circuit computing system according to a particular embodiment of the present invention. The microcomputer 10 is mounted on a central processing unit (CPU) 11, an inter-module bus (IMB) 12, a serial communication interface 13, and a board (on-boar
d) It includes a memory 14, a timer module 15, and a system integration module (SIM) 16. The inter-module bus 12 with multiplexed data, address, and control signal lines as described in detail below
It is connected between and communicates with each of the ten other components. The serial interface 13 is connected to the microcomputer 10 by several serial I / O pins.
And / or external devices and systems for synchronous and / or asynchronous serial data transfer. Memory 14 provides microcomputer 10 with storage for useful software instructions and other data.
Timer module 15 provides various timing functions, such as capturing inputs, comparing outputs, etc., via a number of timer pins and is connected to memory 14 by interface 17. SIM 16 provides an interface between IMB 12 and an external bus, the details of which are described below,
It also provides certain system functions such as clock signal generation and distribution.

The table below shows the signal definitions for all IMB 12 lines and external buses connected to SIM 16. Both of these buses are parallel communication buses.

Note that the signal directions in the table are described for CPU11.

Pin indicated by * above, address pin A1
9 to A23, function code pins FC0 to FC2, bus request pin BR,
The bus permission pin BG and the bus permission recognition pin BGACK can also be used as programmable chip select pins. This function of the microcomputer 10 has nothing to do with the understanding of the present invention. The directions of the signals are described with respect to microcomputer 10.

Among the functions of the SIM 16 are functions that determine when the bus cycle started by the CPU 11 is directed to an external device of the microcomputer 10. This corresponds to the case where the SIM 16 executes an appropriate bus cycle on the external bus and mediates between the internal bus cycle and the external bus cycle. In addition, SIM1
6 has the ability to indicate the internal bus cycle directed to the internal module of the microcomputer 10 via the external bus. This feature is particularly useful for debugging and development purposes.

FIG. 2 shows, in a very simplified manner, the internal structure of the CPU 11 of FIG. Basically, the CPU 11 comprises a micro machine 20, an execution unit 21, a set of registers 22 and a bus
An interface 23 is provided. The micro machine 20
It is bidirectionally connected to the interface 23 and the execution unit 21. The register 22 and the execution unit 21 are connected to each other by an internal bus or the like not shown here.
The execution unit 21 is also bidirectionally connected to the interface 23. The interface 23 is connected to addresses, data, and control signals that constitute the IMB 12.

The micromachine 20 determines the sequence in which the instructions are to be executed, receives the instructions from the interface 23 after the instructions have been called from memory (either the memory module 14 or external memory),
Responsible for instructing 23 to invoke instructions and to read or write operands, and to decode the instructions into a plurality of control signals for use in controlling execution unit 21. As part of the function of the instruction sequence of the micromachine 20, this performs exception handling, including the ability to determine whether to acknowledge an interrupt request received from the IMB 12 via the interface 23. The execution unit 22 is a micro machine
Responsible for the actual execution of the logic, operations and other functions encoded in the instructions received by 20. Register 22
Stores various inputs to the execution unit 21 and operation results of the execution unit 21. IMB interface 23
Is a master-only interface to IMB12. That is, the IMB interface 23 can initiate a read and write cycle of the IMB 12 and allow other masters to initiate this cycle, but not to any of the IMB 12 read or write cycles initiated by other bus masters. Can not respond.

Next, FIG. 3 shows the register 22 shown in FIG. 2 in detail. Registers 22 are eight 32-bit data registers, referred to as D0-D7, seven 32-bit address registers, referred to as A0-A6, USP (stack pointer for user)
And two stack pointers, respectively called SSP (Stack Pointer for Administrator), one 32 called PC
Bit program counter, one 16-bit status register called SR, two 3-bit function code registers called SFC (for source function code) and DFC (for destination function code), respectively, and VB
It has one 32-bit vector base register, called R. These two stack pointers are alternately referenced by the symbols A7 and A7 ', respectively.

The register 22 includes what is called a program model of the CPU 11. The model for the programmer shown here is well known to all users of the 68000 family of microprocessors supplied by Motorola, Inc. of Austin, Texas.

For the purposes of the present invention, only bits 8 to 10 of the status register SR are particularly relevant. I0, I1 and I2
These bits, respectively, have an interrupt mask. These three bits can be encoded into eight different interrupt mask settings and participate in the execution of the prioritized interrupt acknowledgment mechanism. Basically, every interrupt source, internal or external, must reveal its current interrupt priority (level) setting to the CPU 11 in connection with the acknowledgment of the interrupt request. If the requesting interrupt source is set to a higher priority than the current mask value encoded in bits 8 to 10 of the status register, the interrupt is acknowledged. If the priority value is less than or equal to the mask value (except for level 7 interrupts), this interrupt is not acknowledged. Table 3 below shows the coding scheme of the interrupt mask.

The priority of the interrupt request is determined by the levels of the seven interrupt request lines ▲ to ▲. The interrupt source with priority setting 7 is
Use ▲ ▼ to generate an interrupt request,
An interrupt source with priority setting 6 uses ▼ to generate an interrupt request, and so on.

Under normal operating conditions, all interrupt requests are
Will be notified. Interrupt logic internal to CPU 11 compares the priority of each interrupt request with its current mask setting and, if appropriate, initiates an exception handling sequence.

The normal read and write periods of the IMB 12 are described with reference to FIG. 4, which is a timing chart showing these periods. The illustrated signals are IMB12 signals. The signals specified for the external bus are basically the same as those described here. The basic internal read and write cycle of the IMB 12 (that is, the microcomputer 10
Cycle directed to one of its internal modules) occurs over the entire two cycles of CLOCK, ie, at the master system clock signal. The four phases, or crosses, of these clocks that occur during the basic bus cycle are numbered 1 through 4 and correspond to the four states of the bus cycle.

The internal read cycle is started during the state 4 with the affirmation of ▲. At this point, the bus master again
▼ is negated and the address and function code are driven. During this period, IMB12 has ▲ ▼, ▲
▼ and ▲ ▼ are charged in advance.

During the next clock phase, state 1, the bus master asserts ▼ and the slave corresponding to this cycle asserts ▼. In addition, the IMB 12 precharges the data line and ▼ during the state 1 period. At the beginning of state 2, the bus master asserts ▲. The slave may start driving the data line at the same time as the state 2 starts.

The slave must respond to the bus cycle during state 3 by asserting ▲ or the appropriate error signal. At the end of state 3, ▲
The ▼ and error signals are sampled, and if neither is affirmed, the master inserts a wait state (indicated by 3 ^* ) and then returns to state 3 again to sample the ▲ ▼ and error signals.

By the start of state 4, this slave must have started driving the data line, and cancels the affirmation of ▼. This completes the basic internal read cycle.

The basic internal write cycle is similar to that described above, except that ▲ is affirmed in state 4 and the bus master drives data at the beginning of state 2. Otherwise, the write cycle is the same as the read cycle.

The basic external read and write cycles are basically the same as the corresponding internal cycle, but the insertion of the standby state (3 * state) in each cycle is different. This insertion is performed by the SIM 16 to "prevent" the end of the IMB cycle while the later external bus completes its cycle. This external bus has five basic periodic states.

The low power mode is determined for the microcomputer 10, which is started by the CPU 11 executing a specific instruction LPSTOP. This instruction has three words (48 bits total). The first two words have specific bits identifying the LPSTOP instruction (opcode), and the third word has immediate data. When the LPSTOP instruction is received and decoded by the micro machine 20 (FIG. 2), a number of control signals are generated, which cause the execution unit 21 and the bus interface 23 to perform certain tasks. First, one or more control signals are generated, which cause the execution unit 21 to
The direct data part of the instruction is placed in the status register SR. This is the interrupt mask bit (status
This has the effect of resetting (along with other control and condition code bits in the register) to the value indicated in the immediate data area. Next, when one or more control signals are generated, the program counter is incremented to indicate the location of the next instruction to be fetched. Finally, when one or more control signals are generated, this causes the bus interface 23 to execute a special bus cycle, the LPSTOP cycle.

This LPSTOP cycle is basically a normal internal write cycle as described above. The LPSTOP cycle consists of a function code signal (FC0 to FC2) and a certain address signal (A16 to A16).
It is distinguished from the other write cycles by the value of 19).

This function code signal identifies each read or write cycle initiated by CPU 11 as being addressed to one of several possible address spaces. Encoded versions of these various address space and function code signals are shown in Table 4.

In the case of the LPSTOP cycle, the function code signals are all equal to 1, which is the CPU space cycle. Some other CPUs
Space period (eg, breakpoint and interrupt acknowledgment)
Therefore, the address lines A16 to A19 are used to distinguish CPU space periods from each other. LPSTOP
For periods, A19 and A18 are equal to 0, A16 and A17
Is equal to 1.

This LPSTOP cycle is one of the special register access cycles.
It is an example. All special register access periods have the function code described above and an encoding of A16 to A19. The lower 16 address signals indicate which particular register is being accessed. In the preferred embodiment, the only special register implemented is the interrupt mask register in SIM 16, which is the destination of the LPSTOP period. In general, address signals A12-A15 identify the chip, signals A8-A11 identify the module, and A0-A7 identify a particular register that is the target of a particular register access period. In the preferred embodiment, signals A0 through A15 are all equal to one for the LPSTOP period.

Lower three lines of the data bus (DATA0 to DATA2)
Is used to communicate with bits 8 through 10 of the status register (I0-I2) during the LPSTOP period. SIM1
6 responds to the LPSTOP cycle by storing the interrupt mask bit in its interrupt mask register.

The LPSTOP cycle is primarily intended to notify the internal module that a low power mode input is imminent, and to communicate an interrupt mask bit to the SIM 16. However, external devices of the microcomputer 10 may also need to be notified of the arrival of the low power mode. Therefore, if the external bus is not controlled by an external bus master, the LPST
The OP cycle is performed by the SIM 16 on the external bus so that, if necessary, the external device can prepare for a low power mode.

In addition to storing the interrupt mask bits, the SIM 16 responds to the LPSTOP cycle by stopping the IMB clock signal, CLOCK. CPU 11 and all other internal modules of microcomputer 10 use CLOCK as the sole source of basic internal timing. Therefore,
If the CLOCK stops, all these modules also stop. This greatly reduces power consumption. The SIM 16 continues to generate clock signals for its own use and remains "wake" during the low power mode.
Externally supplied clock signal during low power mode
CLK may or may not stop depending on the state of the control bits set in the SIM 16 under the control of the CPU 11.

The event that can end the low-power mode is reset (the L has been in the predetermined period L).
External devices with pins) and interrupts having a priority high enough that they are not masked by the interrupt mask bits stored in the interrupt mask register of SIM16. Since all the internal modules other than the SIM 16 are stopped during the low power mode, none of the modules can generate an interrupt signal for terminating the low power state. However, the SIM 16 itself has some kind of monitor capable of generating an interrupt (eg, a watchdog timer, a periodic interrupt circuit, etc.), and the SIM 16 is active during the low power mode, so the low power mode Can be generated in the microcomputer 10. For the specific embodiment described above, SI
Of the interrupt sources in M16, only the periodic interrupt circuit is active during the low power mode. Of course, it is also possible for an external circuit to be the source of the interrupt.

While operation is in the low power mode, the SIM 16 simply waits for either a reset or an interrupt event. In any reset event, SIM16 re-generates the CLOCK signal, and ▲
▼ affirm the signal to resume normal program execution. Any interrupt event having a priority high enough to exceed the level masked by the interrupt mask bit passed to SIM 16 by the LPSTOP period allows exit from low power mode. In the case of an interrupt, SIM16 re-generates CLOCK and returns
Deliver the interrupt request to CPU11 with the ▼ or ▲ ▼ line. As with any other such request, CPU 11 executes the appropriate exception handling routine in response to this interrupt request and returns to normal program execution with the instruction following the LPSTOP instruction that initiated the low power mode.

The interrupt mask register in the SIM 16 is ignored except during the period of the low power state following the execution of the LPSTOP instruction. All internally generated interrupts are sent directly to the CPU 11 via the IMB 12. CPU 11 makes the necessary comparison to determine whether the interrupt signal is acknowledged. All externally generated interrupts are sent unconditionally by the SIM 16 from the external bus interrupt line directly to the IMB 12 interrupt line.

Decoupling the low power mode exit logic from the normal reset and interrupt logic of the CPU will
Can be completely shut down, thus saving considerable power. By having the system integration module perform a separate mask-level comparison, lower priority interrupts are completely ignored, eliminating the need to “wake up” the CPU to make the comparison. The present invention is not limited to such situations where the setting of the interrupt mask is a significant determinant of exiting the low power mode. This may be any other conditional evaluation normally performed by the central processing unit, but is preferably performed by any other part of the system during operation in the low power mode. Further, the details of the LPSTOP cycle described above are not important to the functioning of the present invention. Thus, exit from the low power mode can replace the disclosed LPSTOP bus cycle with any communication means qualified from the central processing unit to some portion of the system that is active during the low power state.

Although the present invention has been shown and described with reference to particular embodiments, various modifications of the disclosed embodiment are possible without departing from the spirit and scope of the invention. Traders understand. For example, although the invention has been disclosed in the context of a microcomputer having certain modules, any of these modules may be replaced by other modules having different functionality. Further, while the preferred central processing unit is a microcoded machine, the present invention can be readily implemented on hardwired devices. Further, the particular embodiment described above implements clock signal stopping by stopping the generation of these signals at the source of the clock signal. In another embodiment, the generation and distribution of the clock signal continues during the low power mode and also generates an LPSTOP control signal, which may be distributed to all internal modules. In each module, the logic circuit is
Responding to the LPSTOP control signal by stopping the module by blocking the clock signal, or by keeping the module running during the low power mode by not blocking the clock signal. This alternative embodiment increases power consumption during the low power mode,
Flexibility is increased by allowing some modules to continue operation during the low power mode.

[Brief description of the drawings]

FIG. 1 is a block diagram of an integrated circuit digital computing system according to a particular embodiment of the present invention. FIG. 2 is a block diagram of a central processing unit of the computing system shown in FIG. FIG. 3 is an explanatory diagram showing a set of registers of the central processing unit shown in FIG. FIG. 4 is a timing chart showing some bus cycles executed by the central processing unit shown in FIG. (Explanation of main symbols) 10: microcomputer, 11: central processing unit (CPU), 12: bus between modules (IMB), 13: communication interface, 14: on-board memory, 15: timer / Module 16 System integration module (SIM) 20 Micro machine 21 Execution unit 22 Register set 23 Bus interface

──────────────────────────────────────────────────の Continued on the front page (72) Inventor John P. Dunn, Texas, United States 78737, Austin, Granada Hills Drive 9206 (72) Inventor Bradley G. Verges, United States 78749, Texas, Austin, Cana・ Cube 5014A (56) References JP-A-58-222349 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G06F 1/04 G06F 15/78

Claims (5)

(57) [Claims] 1. An integrated circuit computing system, comprising: (a) a central processing unit, further comprising: a clock signal input terminal; an interrupt signal input terminal; first register means for storing an interrupt mask value; First comparing means coupled to receive a regular and periodic clock signal from an input terminal and comparing a priority level of an interrupt signal received at the interrupt signal input terminal with the interrupt mask value;
The comparison means functions only while a regular and periodic clock signal is received at the clock signal input terminal, and only when the regular and periodic clock signal is received at the clock signal input terminal. Executing means for executing the instruction and not executing the instruction while a regular and periodic clock signal is not received at the clock signal input terminal, the execution means further executing the first instruction; Bus interface means having a plurality of bus interface terminals including an address terminal and a data terminal, the bus interface means comprising: a means for generating a first control signal only when a first instruction is executed; Means are coupled to receive the first control signal from the executing means, and the bus interface means Providing a signal indicating the interrupt mask value to a part of the plurality of bus interface terminals only when the first control signal is received from the execution means; (b) An internal bus having address lines coupled to the address terminals of the bus interface means of the central processing unit and having data lines coupled to the data terminals of the bus interface means of the central processing unit; A first plurality of bus interface terminals including an internal address terminal and an internal data terminal respectively coupled to the address line and the data line, and coupling the integrated circuit computing system to a device external to the integrated circuit computing system; Integrated module having a plurality of external interface terminals for And clock signal generating means coupled to a first clock signal output terminal of the integrated module, wherein the first clock signal output terminal of the integrated module is the clock signal input terminal of the central processing unit Wherein the clock signal generator further provides a regular and periodic clock signal to the first clock signal output terminal of the integrated module and thereby to the clock signal input terminal of the central processing unit. And when the bus interface means of the central processing unit provides a signal indicating the interrupt mask value to the part of the plurality of bus interface terminals, the regular and periodic clock signal is transmitted to the integrated module. Stopping providing to the first clock signal output terminal and providing a second control signal The first of the integrated modules when
Means for resuming providing the clock signal to a clock signal output terminal of the integrated module, coupled to the first plurality of bus interface terminals of the integrated module, only in response to the first control signal Second register means for receiving a signal indicating the interrupt mask value from the first plurality of bus interface terminals, and thereafter storing the signal indicating the interrupt mask value, and setting the priority level of the interrupt signal to the second The second control signal is supplied to the clock signal generator based on a result of comparing the signal stored in the register means and comparing the priority level of the interrupt signal with the signal stored in the second register means. A second comparing means provided in an integrated manner,
The second comparing means is provided only after the bus interface means of the central processing unit gives a signal indicating the interrupt mask value to the part of the plurality of bus interface terminals of the central processing unit, and An integrated circuit computing system comprising: an integrated module comprising: a device that operates until a control signal is generated. 2. The system of claim 1, further comprising a clock signal input terminal coupled to the first clock signal output terminal of the integrated module, and an interrupt signal output terminal coupled to the interrupt signal input terminal of the central processing unit. The integrated circuit computing system according to claim 1, comprising at least one module having: 3. The integrated module further comprises: first means for receiving an interrupt signal from one of the plurality of external interface terminals; and the interrupt signal of the central processing unit coupled to the first means. A second means for providing an interrupt signal received by the first means to an input terminal; and an interrupt signal received by the first means coupled to the first means and to the second comparing means. 3. The integrated circuit computing system according to claim 2, comprising: third means for providing. 4. The integrated module is further coupled to receive a clock signal from the clock signal generator for providing an interrupt signal to the interrupt signal input terminal of the central processing unit and to the second comparing means. The integrated circuit calculation system according to claim 2, further comprising: interrupt signal generation means. 5. A method for executing a specific instruction in a digital computing system (10), said digital computing system (10) comprising a central processing unit (11) and an integrated module (11) coupled by a communication bus (12). 16)
The central processing unit has a storage circuit (22) for storing an interrupt mask value, the method comprising: the central processing unit (11) receiving the specific instruction; the central processing unit (11). Decoding said specific instruction, and said central processing unit (11) initiating a write bus cycle during execution of said specific instruction, said method further comprising: Transferring the interrupt mask value and the predetermined signal from the central processing unit (11) to the integrated module (16) by the communication bus (12) in between; and transmitting the interrupt mask value and the predetermined signal from the communication bus (12). Stopping the integrated module (16) from providing a clock signal to the central processing unit (11) in response to receiving the predetermined signal; Digital computing system characterized by having a (1
Method to execute a specific instruction in 0).