JPS5692618A - Clock switching and controlling method - Google Patents

Clock switching and controlling method

Info

Publication number
JPS5692618A
JPS5692618A JP17247879A JP17247879A JPS5692618A JP S5692618 A JPS5692618 A JP S5692618A JP 17247879 A JP17247879 A JP 17247879A JP 17247879 A JP17247879 A JP 17247879A JP S5692618 A JPS5692618 A JP S5692618A
Authority
JP
Japan
Prior art keywords
main memory
cpus
internal information
control unit
memory control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17247879A
Other languages
Japanese (ja)
Inventor
Masayuki Okawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17247879A priority Critical patent/JPS5692618A/en
Publication of JPS5692618A publication Critical patent/JPS5692618A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To enable to prevent the error in computer systems, by saving the internal information of CPU at the switching of clock and returning the internal information saved after clock switching.
CONSTITUTION: If a failure is taken place to a main memory control unit 2-0, a service processor 5 saves the internal information of CPUs 3-0, 3-1 and it reconnects the CPUs 3-0, 3-1 and channel processors 4-0, 4-1 to a main memory control unit 2-1. As a result, the oscillator of a main memory control unit 2-1 supplies clock to the system. After the reconnection, the processor 5 resets the internal information of CPUs 3-0, 3-1 and channel processor 4-0, 4-1, and returns the internal information of the CPUs 3-0 and 3-1 saved to the original location after that. Then, the processor 5 to bring the main memory 1 ON-line connects the main memory 1 to the main memory control unit 2-1 to start the CPUs 3-0, 3-1.
COPYRIGHT: (C)1981,JPO&Japio
JP17247879A 1979-12-26 1979-12-26 Clock switching and controlling method Pending JPS5692618A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17247879A JPS5692618A (en) 1979-12-26 1979-12-26 Clock switching and controlling method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17247879A JPS5692618A (en) 1979-12-26 1979-12-26 Clock switching and controlling method

Publications (1)

Publication Number Publication Date
JPS5692618A true JPS5692618A (en) 1981-07-27

Family

ID=15942723

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17247879A Pending JPS5692618A (en) 1979-12-26 1979-12-26 Clock switching and controlling method

Country Status (1)

Country Link
JP (1) JPS5692618A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009273985A (en) * 2008-05-13 2009-11-26 Sharp Corp Disassembling apparatus of thin-screen television and disassembling method of thin-screen television

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009273985A (en) * 2008-05-13 2009-11-26 Sharp Corp Disassembling apparatus of thin-screen television and disassembling method of thin-screen television

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