SE8902191L - Saett och anordning foer teorembevisning - Google Patents

Saett och anordning foer teorembevisning

Info

Publication number
SE8902191L
SE8902191L SE8902191A SE8902191A SE8902191L SE 8902191 L SE8902191 L SE 8902191L SE 8902191 A SE8902191 A SE 8902191A SE 8902191 A SE8902191 A SE 8902191A SE 8902191 L SE8902191 L SE 8902191L
Authority
SE
Sweden
Prior art keywords
variables
formula
triplets
checking
called
Prior art date
Application number
SE8902191A
Other languages
Unknown language ( )
English (en)
Other versions
SE8902191D0 (sv
SE467076B (sv
Inventor
Gunnar Martin Natan Staalmarck
Original Assignee
Gunnar Martin Natanael Staalma
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gunnar Martin Natanael Staalma filed Critical Gunnar Martin Natanael Staalma
Priority to SE8902191A priority Critical patent/SE467076B/sv
Publication of SE8902191D0 publication Critical patent/SE8902191D0/sv
Priority to DE69020438T priority patent/DE69020438T2/de
Priority to EP90850184A priority patent/EP0403454B1/en
Priority to CA002018828A priority patent/CA2018828C/en
Priority to US07/537,937 priority patent/US5276897A/en
Priority to JP2157416A priority patent/JP3046611B2/ja
Publication of SE8902191L publication Critical patent/SE8902191L/sv
Publication of SE467076B publication Critical patent/SE467076B/sv

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3323—Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N5/00—Computing arrangements using knowledge-based models
    • G06N5/01—Dynamic search techniques; Heuristics; Dynamic trees; Branch-and-bound
    • G06N5/013—Automatic theorem proving
SE8902191A 1989-06-16 1989-06-16 Saett och anordning foer teorembevisning SE467076B (sv)

Priority Applications (6)

Application Number Priority Date Filing Date Title
SE8902191A SE467076B (sv) 1989-06-16 1989-06-16 Saett och anordning foer teorembevisning
DE69020438T DE69020438T2 (de) 1989-06-16 1990-05-17 Verfahren und Vorrichtung zum Prüfen von Aussagelogiktheoremen in der Systemanalyse.
EP90850184A EP0403454B1 (en) 1989-06-16 1990-05-17 Method and apparatus for checking propositional logic theorems in system analysis
CA002018828A CA2018828C (en) 1989-06-16 1990-06-12 Determining propositional logic theorems by applying values and rules to triplets that are generated from a boolean formula
US07/537,937 US5276897A (en) 1989-06-16 1990-06-14 System for determining propositional logic theorems by applying values and rules to triplets that are generated from boolean formula
JP2157416A JP3046611B2 (ja) 1989-06-16 1990-06-15 トートロジーチェック装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE8902191A SE467076B (sv) 1989-06-16 1989-06-16 Saett och anordning foer teorembevisning

Publications (3)

Publication Number Publication Date
SE8902191D0 SE8902191D0 (sv) 1989-06-16
SE8902191L true SE8902191L (sv) 1990-12-17
SE467076B SE467076B (sv) 1992-05-18

Family

ID=20376307

Family Applications (1)

Application Number Title Priority Date Filing Date
SE8902191A SE467076B (sv) 1989-06-16 1989-06-16 Saett och anordning foer teorembevisning

Country Status (6)

Country Link
US (1) US5276897A (sv)
EP (1) EP0403454B1 (sv)
JP (1) JP3046611B2 (sv)
CA (1) CA2018828C (sv)
DE (1) DE69020438T2 (sv)
SE (1) SE467076B (sv)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5680518A (en) * 1994-08-26 1997-10-21 Hangartner; Ricky D. Probabilistic computing methods and apparatus
US5974462A (en) * 1997-03-28 1999-10-26 International Business Machines Corporation Method and apparatus for controlling the number of servers in a client/server system
US7216306B1 (en) 1999-03-24 2007-05-08 Zhe Li Checkpoint restart method using condensed partial results by determining boolean constant subsets
US6415430B1 (en) 1999-07-01 2002-07-02 Nec Usa, Inc. Method and apparatus for SAT solver architecture with very low synthesis and layout overhead
US7073143B1 (en) 2000-11-06 2006-07-04 Cadence Design Systems, Inc. Solving constraint satisfiability problem for circuit designs
US6618841B1 (en) 2000-11-06 2003-09-09 Verplex Systems, Inc. Non-assignable signal support during formal verification of circuit designs
US7653520B2 (en) * 2002-07-19 2010-01-26 Sri International Method for combining decision procedures with satisfiability solvers
US7120569B2 (en) * 2003-05-19 2006-10-10 Javier Armando Arroyo-Figueroa Sequential machine for solving boolean satisfiability (SAT) problems in linear time
US8001072B2 (en) * 2008-06-19 2011-08-16 Microsoft Corporation Determining satisfiability of a function with arbitrary domain constraints
US9685959B2 (en) 2014-09-12 2017-06-20 Ecole Polytechnique Federale De Lausanne (Epfl) Method for speeding up boolean satisfiability

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3043563A1 (de) * 1980-11-15 1982-06-24 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Verfahren zur auswertung boolescher ausdruecke
US4504236A (en) * 1981-06-11 1985-03-12 Shea Zellweger Devices for displaying or performing operations in a two-valued system
US4698751A (en) * 1984-07-13 1987-10-06 Ford Aerospace & Communications Corporation Systolic array for solving cyclic loop dependent algorithms
US4722071A (en) * 1985-04-19 1988-01-26 Pertron Controls, Corporation Compiler for evaluating Boolean expressions
JPS63229857A (ja) * 1987-03-19 1988-09-26 Sanyo Electric Co Ltd 静電破壊保護回路
DE3807813A1 (de) * 1988-03-10 1989-09-21 Thomae Gmbh Dr K Neue benzocycloheptenderivate, diese verbindungen enthaltende arzneimittel und verfahren zu deren herstellung
JPH01231166A (ja) * 1988-03-11 1989-09-14 Fujitsu Ltd 日本語文章処理方式

Also Published As

Publication number Publication date
US5276897A (en) 1994-01-04
SE8902191D0 (sv) 1989-06-16
JP3046611B2 (ja) 2000-05-29
SE467076B (sv) 1992-05-18
DE69020438D1 (de) 1995-08-03
EP0403454B1 (en) 1995-06-28
DE69020438T2 (de) 1995-12-14
EP0403454A1 (en) 1990-12-19
JPH0329034A (ja) 1991-02-07
CA2018828C (en) 1998-05-05
CA2018828A1 (en) 1990-12-16

Similar Documents

Publication Publication Date Title
SE8902191L (sv) Saett och anordning foer teorembevisning
Lockett et al. A scheduling problem involving sequence dependent changeover times
DE3876741D1 (de) Vorrichtungen und verfahren zum beglaubigen von vollmachten oder nachrichten mittels eines null-kenntnis-probe-systems und zum unterschreiben von nachrichten.
EP0496928A3 (en) Compounding preprocessor for cache
DE69622875T2 (de) System und verfahren zum generieren von anwendungsprogrammen und deren dokumentation
ATE32275T1 (de) Verfahren und vorrichtung zur verifizierung einer persoenlichen identifikationsnummer und zur pruefung einer in einem identifikationsorgan gespeicherten nummernserie.
Verpeaux et al. A modern approach of large computer codes for structural analysis
EP0669573A4 (en) RULE GENERATOR APPARATUS AND METHOD.
DE3787900D1 (de) Verfahren und Gerät zur Erzeugung von Prüfungs-Byten zur Fehlerdetektion für einen Datenblock.
US5202960A (en) Method and apparatus for plotting polygon edges on a pixelized grid
ATE251781T1 (de) Trainingsverfahren und gerät zur erzeugung eines neues neurons
Amyeen et al. Fault equivalence identification using redundancy information and static and dynamic extraction
AR241391A1 (es) Un dispositivo de entrada interactivo concurrentemente con una pluralidad de terminales virtuales.
DE69230520D1 (de) Verfahren und Anordung zur Erzeugung von Summeinformation-/Rundungskontrolle-Signal
ATE72489T1 (de) Verfahren zum betrieb eines signaltechnisch sicheren mehrrechnersystems mit mehreren signaltechnisch nicht sicheren ein/ausgabebaugruppen.
JPS4952547A (sv)
JPS58137060A (ja) Ｌｓｉ搭載パツケ−ジの診断方式
SU737947A1 (ru) Программирующа среда
Shine The relative efficiency of test selection methods in cross-validation on generated data
DE3889356T2 (de) Mustererkennungsgerät, das nach einer zusammengesetzten Ähnlichkeitsmethode arbeitet.
MILLER Preliminary design and implementation of a method for validating evolving Ada compilers[M. S. Thesis]
JPS63118844A (ja) シミユレ−シヨン処理装置
JPS59116064A (ja) 論理回路試験装置
Zislis Semantic decomposition of computer programs: a program test aid.
JPS6481043A (en) System for testing data processor

Legal Events

Date Code Title Description
NAL Patent in force

Ref document number: 8902191-9

Format of ref document f/p: F

NUG Patent has lapsed