SE8804196L - Foerfarande och anordning foer att restaurera en datasignal - Google Patents

Foerfarande och anordning foer att restaurera en datasignal

Info

Publication number
SE8804196L
SE8804196L SE8804196A SE8804196A SE8804196L SE 8804196 L SE8804196 L SE 8804196L SE 8804196 A SE8804196 A SE 8804196A SE 8804196 A SE8804196 A SE 8804196A SE 8804196 L SE8804196 L SE 8804196L
Authority
SE
Sweden
Prior art keywords
signal
delay means
time
sensing
time steps
Prior art date
Application number
SE8804196A
Other languages
Unknown language ( )
English (en)
Other versions
SE8804196D0 (sv
SE469203B (sv
Inventor
M Hedberg
Original Assignee
Ellemtel Utvecklings Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ellemtel Utvecklings Ab filed Critical Ellemtel Utvecklings Ab
Priority to SE8804196A priority Critical patent/SE469203B/sv
Publication of SE8804196D0 publication Critical patent/SE8804196D0/sv
Priority to US07/429,651 priority patent/US5054038A/en
Priority to EP89850381A priority patent/EP0369966B1/en
Priority to DE89850381T priority patent/DE68909374T2/de
Priority to AT89850381T priority patent/ATE95017T1/de
Priority to ES89850381T priority patent/ES2045558T3/es
Priority to JP1297793A priority patent/JP2948841B2/ja
Priority to AU45310/89A priority patent/AU628104B2/en
Publication of SE8804196L publication Critical patent/SE8804196L/sv
Publication of SE469203B publication Critical patent/SE469203B/sv

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0041—Delay of data signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Manipulation Of Pulses (AREA)
  • Communication Control (AREA)
  • Pulse Circuits (AREA)
SE8804196A 1988-11-18 1988-11-18 Foerfarande och anordning foer att restaurera en datasignal SE469203B (sv)

Priority Applications (8)

Application Number Priority Date Filing Date Title
SE8804196A SE469203B (sv) 1988-11-18 1988-11-18 Foerfarande och anordning foer att restaurera en datasignal
US07/429,651 US5054038A (en) 1988-11-18 1989-10-31 Method and apparatus for restoring data
EP89850381A EP0369966B1 (en) 1988-11-18 1989-11-02 Method and apparatus for restoring data
DE89850381T DE68909374T2 (de) 1988-11-18 1989-11-02 Methode und Vorrichtung zur Wiederherstellung eines Datensignales.
AT89850381T ATE95017T1 (de) 1988-11-18 1989-11-02 Methode und vorrichtung zur wiederherstellung eines datensignales.
ES89850381T ES2045558T3 (es) 1988-11-18 1989-11-02 Metodo y aparato para restaurar datos.
JP1297793A JP2948841B2 (ja) 1988-11-18 1989-11-17 データを復元する方法と装置
AU45310/89A AU628104B2 (en) 1988-11-18 1989-11-17 Method and apparatus for restoring data

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE8804196A SE469203B (sv) 1988-11-18 1988-11-18 Foerfarande och anordning foer att restaurera en datasignal

Publications (3)

Publication Number Publication Date
SE8804196D0 SE8804196D0 (sv) 1988-11-18
SE8804196L true SE8804196L (sv) 1990-05-19
SE469203B SE469203B (sv) 1993-05-24

Family

ID=20374006

Family Applications (1)

Application Number Title Priority Date Filing Date
SE8804196A SE469203B (sv) 1988-11-18 1988-11-18 Foerfarande och anordning foer att restaurera en datasignal

Country Status (8)

Country Link
US (1) US5054038A (sv)
EP (1) EP0369966B1 (sv)
JP (1) JP2948841B2 (sv)
AT (1) ATE95017T1 (sv)
AU (1) AU628104B2 (sv)
DE (1) DE68909374T2 (sv)
ES (1) ES2045558T3 (sv)
SE (1) SE469203B (sv)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5164677A (en) * 1990-01-16 1992-11-17 Digital Equipment Corporation Method and apparatus for synchronizing signals
US5192886A (en) * 1990-03-15 1993-03-09 Hewlett-Packard Company Sub-nanosecond calibrated delay line structure
JP2597739B2 (ja) * 1990-08-24 1997-04-09 株式会社東芝 信号遅延回路、クロック信号発生回路及び集積回路システム
EP0476585B1 (en) * 1990-09-18 1998-08-26 Fujitsu Limited Electronic device using a reference delay generator
EP0553744B1 (en) * 1992-01-31 2001-03-28 Konica Corporation Signal delay device
US5408200A (en) * 1992-12-18 1995-04-18 Storage Technology Corporation Intelligent phase detector
ES2103106T3 (es) * 1993-02-25 1997-08-16 At & T Corp Linea de retardo variable de amplio margen y oscilador en anillo.
US5479129A (en) * 1993-11-24 1995-12-26 At&T Corp. Variable propagation delay digital signal inverter
US5515403A (en) * 1994-06-21 1996-05-07 Dsc Communications Corporation Apparatus and method for clock alignment and switching
EP0720291B1 (en) * 1994-12-20 2002-04-17 Nec Corporation Delay circuit device
JP3050162B2 (ja) * 1997-04-04 2000-06-12 日本電気株式会社 狭撃型同期式遅延回路
US6777995B1 (en) * 1999-02-26 2004-08-17 Micron Technology, Inc. Interlaced delay-locked loops for controlling memory-circuit timing
JP3478284B2 (ja) * 2001-08-10 2003-12-15 ソニー株式会社 半導体装置
US7082172B1 (en) * 2002-02-05 2006-07-25 Alliant Techsystems Inc. Digital signal gating apparatus and method in a pulse receiver system
KR101030768B1 (ko) * 2004-08-26 2011-04-27 삼성전자주식회사 소비전력이 적고 고주파 동작이 가능한 광범위 지연동기루프 회로 및 이를 구비하는 광학 구동 시스템
US7724811B2 (en) * 2006-09-26 2010-05-25 Advantest Corporation Delay circuit, jitter injection circuit, and test apparatus

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1355495A (en) * 1970-08-18 1974-06-05 Cossor Ltd A C Apparatus for clocking digital data
US3694752A (en) * 1971-03-18 1972-09-26 North American Rockwell High speed transmission receiver utilizing fine receiver timing and carrier phase recovery
US4190807A (en) * 1978-07-03 1980-02-26 Rockwell International Corporation Sampled error phaselock or frequencylock systems
JPS60229521A (ja) * 1984-04-27 1985-11-14 Sony Tektronix Corp デジタル信号遅延回路
US4695805A (en) * 1985-05-13 1987-09-22 Online Computer Systems Inc. Apparatus for generating signals synchronized to an unstable external signal
US4922141A (en) * 1986-10-07 1990-05-01 Western Digital Corporation Phase-locked loop delay line
US4755704A (en) * 1987-06-30 1988-07-05 Unisys Corporation Automatic clock de-skewing apparatus
US4829258A (en) * 1987-09-03 1989-05-09 Intel Corporation Stabilized phase locked loop

Also Published As

Publication number Publication date
ES2045558T3 (es) 1994-01-16
DE68909374T2 (de) 1994-01-13
EP0369966A1 (en) 1990-05-23
JP2948841B2 (ja) 1999-09-13
EP0369966B1 (en) 1993-09-22
AU4531089A (en) 1990-05-24
US5054038A (en) 1991-10-01
JPH02260730A (ja) 1990-10-23
AU628104B2 (en) 1992-09-10
ATE95017T1 (de) 1993-10-15
SE8804196D0 (sv) 1988-11-18
SE469203B (sv) 1993-05-24
DE68909374D1 (de) 1993-10-28

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