SE428508B - Sett att forma total dielektrisk isolering i en kiselstruktur - Google Patents

Sett att forma total dielektrisk isolering i en kiselstruktur

Info

Publication number
SE428508B
SE428508B SE7802044A SE7802044A SE428508B SE 428508 B SE428508 B SE 428508B SE 7802044 A SE7802044 A SE 7802044A SE 7802044 A SE7802044 A SE 7802044A SE 428508 B SE428508 B SE 428508B
Authority
SE
Sweden
Prior art keywords
layer
silicon
surface layer
regions
oxidation
Prior art date
Application number
SE7802044A
Other languages
English (en)
Swedish (sv)
Other versions
SE7802044L (sv
Inventor
H B Pogge
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of SE7802044L publication Critical patent/SE7802044L/xx
Publication of SE428508B publication Critical patent/SE428508B/sv

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02203Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314Inorganic layers
    • H01L21/316Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604Deposition from a gas or vapour
    • H01L21/31608Deposition of SiO2
    • H01L21/31612Deposition of SiO2 on a silicon body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314Inorganic layers
    • H01L21/316Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/3165Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
    • H01L21/31654Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
    • H01L21/31658Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe
    • H01L21/31662Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe of silicon in uncombined form
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/7627Vertical isolation by full isolation by porous oxide silicon, i.e. FIPOS techniques
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283Lateral isolation by refilling of trenches with dielectric material
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/051Etching
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/131Reactive ion etching rie
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S205/00Electrolysis: processes, compositions used therein, and methods of preparing the compositions
    • Y10S205/92Electrolytic coating of circuit board or printed circuit, other than selected area coating

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Formation Of Insulating Films (AREA)
SE7802044A 1977-02-24 1978-02-22 Sett att forma total dielektrisk isolering i en kiselstruktur SE428508B (sv)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/771,593 US4104090A (en) 1977-02-24 1977-02-24 Total dielectric isolation utilizing a combination of reactive ion etching, anodic etching, and thermal oxidation

Publications (2)

Publication Number Publication Date
SE7802044L SE7802044L (sv) 1978-08-25
SE428508B true SE428508B (sv) 1983-07-04

Family

ID=25092322

Family Applications (1)

Application Number Title Priority Date Filing Date
SE7802044A SE428508B (sv) 1977-02-24 1978-02-22 Sett att forma total dielektrisk isolering i en kiselstruktur

Country Status (11)

Country Link
US (1) US4104090A (es)
JP (1) JPS53105988A (es)
BR (1) BR7801029A (es)
CA (1) CA1092252A (es)
DE (1) DE2805169A1 (es)
ES (1) ES466901A1 (es)
FR (1) FR2382096A1 (es)
GB (1) GB1544393A (es)
IT (1) IT1113108B (es)
NL (1) NL7802011A (es)
SE (1) SE428508B (es)

Families Citing this family (70)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1068248B (it) * 1976-11-16 1985-03-21 Selenia Ind Elettroniche Procedimento per la realizzazione di dispositivi a semiconduttore passivati con dissipatore di calore integrato
US4264382A (en) * 1978-05-25 1981-04-28 International Business Machines Corporation Method for making a lateral PNP or NPN with a high gain utilizing reactive ion etching of buried high conductivity regions
US4234362A (en) * 1978-11-03 1980-11-18 International Business Machines Corporation Method for forming an insulator between layers of conductive material
US4256514A (en) * 1978-11-03 1981-03-17 International Business Machines Corporation Method for forming a narrow dimensioned region on a body
US4214946A (en) * 1979-02-21 1980-07-29 International Business Machines Corporation Selective reactive ion etching of polysilicon against SiO2 utilizing SF6 -Cl2 -inert gas etchant
US4238278A (en) * 1979-06-14 1980-12-09 International Business Machines Corporation Polycrystalline silicon oxidation method for making shallow and deep isolation trenches
US4234357A (en) * 1979-07-16 1980-11-18 Trw Inc. Process for manufacturing emitters by diffusion from polysilicon
US4307180A (en) * 1980-08-22 1981-12-22 International Business Machines Corp. Process of forming recessed dielectric regions in a monocrystalline silicon substrate
EP0048175B1 (en) * 1980-09-17 1986-04-23 Hitachi, Ltd. Semiconductor device and method of manufacturing the same
EP0059264A1 (en) * 1981-03-02 1982-09-08 Rockwell International Corporation NPN Type lateral transistor with minimal substrate operation interference and method for producing same
EP0059796A1 (en) * 1981-03-02 1982-09-15 Rockwell International Corporation NPN lateral transistor isolated from a substrate by orientation-dependent etching, and method of making it
EP0069191A1 (en) * 1981-06-25 1983-01-12 Rockwell International Corporation Complementary NPN and PNP lateral transistors separated from substrate by intersecting slots filled with substrate oxide for minimal interference therefrom and method for producing same
US4532701A (en) * 1981-08-21 1985-08-06 Tokyo Shibaura Denki Kabushiki Kaisha Method of manufacturing semiconductor device
CA1186808A (en) * 1981-11-06 1985-05-07 Sidney I. Soclof Method of fabrication of dielectrically isolated cmos device with an isolated slot
US4380865A (en) * 1981-11-13 1983-04-26 Bell Telephone Laboratories, Incorporated Method of forming dielectrically isolated silicon semiconductor materials utilizing porous silicon formation
US4488349A (en) * 1982-04-09 1984-12-18 Nissan Motor Company, Limited Method of repairing shorts in parallel connected vertical semiconductor devices by selective anodization
JPS58192344A (ja) * 1982-05-07 1983-11-09 Nippon Telegr & Teleph Corp <Ntt> 半導体装置及びその製造方法
US4502913A (en) * 1982-06-30 1985-03-05 International Business Machines Corporation Total dielectric isolation for integrated circuits
US4459181A (en) * 1982-09-23 1984-07-10 Eaton Corporation Semiconductor pattern definition by selective anodization
FR2559960B1 (fr) * 1984-02-20 1987-03-06 Solems Sa Procede de formation de circuits electriques en couche mince et produits obtenus
US4532700A (en) * 1984-04-27 1985-08-06 International Business Machines Corporation Method of manufacturing semiconductor structures having an oxidized porous silicon isolation layer
FR2564241B1 (fr) * 1984-05-09 1987-03-27 Bois Daniel Procede de fabrication de circuits integres du type silicium sur isolant
US4628591A (en) * 1984-10-31 1986-12-16 Texas Instruments Incorporated Method for obtaining full oxide isolation of epitaxial islands in silicon utilizing selective oxidation of porous silicon
US4627883A (en) * 1985-04-01 1986-12-09 Gte Laboratories Incorporated Method of forming an isolated semiconductor structure
US4648173A (en) * 1985-05-28 1987-03-10 International Business Machines Corporation Fabrication of stud-defined integrated circuit structure
US4643804A (en) * 1985-07-25 1987-02-17 At&T Bell Laboratories Forming thick dielectric at the bottoms of trenches utilized in integrated-circuit devices
US4653177A (en) * 1985-07-25 1987-03-31 At&T Bell Laboratories Method of making and selectively doping isolation trenches utilized in CMOS devices
US4685198A (en) * 1985-07-25 1987-08-11 Matsushita Electric Industrial Co., Ltd. Method of manufacturing isolated semiconductor devices
EP0225519A3 (en) * 1985-12-06 1989-12-06 Texas Instruments Incorporated High definition anodized sublayer boundary
US4810667A (en) * 1987-04-28 1989-03-07 Texas Instruments Incorporated Dielectric isolation using isolated silicon by limited anodization of an N+ epitaxially defined sublayer in the presence of a diffusion under film layer
US4849370A (en) * 1987-12-21 1989-07-18 Texas Instruments Incorporated Anodizable strain layer for SOI semiconductor structures
US4982263A (en) * 1987-12-21 1991-01-01 Texas Instruments Incorporated Anodizable strain layer for SOI semiconductor structures
JPS63232350A (ja) * 1988-02-18 1988-09-28 Nippon Telegr & Teleph Corp <Ntt> 半導体装置
US5091326A (en) * 1988-03-02 1992-02-25 Advanced Micro Devices, Inc. EPROM element employing self-aligning process
US5225374A (en) * 1988-05-13 1993-07-06 The United States Of America As Represented By The Secretary Of The Navy Method of fabricating a receptor-based sensor
US5111221A (en) * 1988-05-13 1992-05-05 United States Of America As Represented By The Secretary Of The Navy Receptor-based sensor
US4910165A (en) * 1988-11-04 1990-03-20 Ncr Corporation Method for forming epitaxial silicon on insulator structures using oxidized porous silicon
US5023200A (en) * 1988-11-22 1991-06-11 The United States Of America As Represented By The United States Department Of Energy Formation of multiple levels of porous silicon for buried insulators and conductors in silicon device technologies
US5057022A (en) * 1989-03-20 1991-10-15 Miller Robert O Method of making a silicon integrated circuit waveguide
US4927781A (en) * 1989-03-20 1990-05-22 Miller Robert O Method of making a silicon integrated circuit waveguide
US5156896A (en) * 1989-08-03 1992-10-20 Alps Electric Co., Ltd. Silicon substrate having porous oxidized silicon layers and its production method
US5132765A (en) * 1989-09-11 1992-07-21 Blouse Jeffrey L Narrow base transistor and method of fabricating same
US5008207A (en) * 1989-09-11 1991-04-16 International Business Machines Corporation Method of fabricating a narrow base transistor
US5110755A (en) * 1990-01-04 1992-05-05 Westinghouse Electric Corp. Process for forming a component insulator on a silicon substrate
US5277769A (en) * 1991-11-27 1994-01-11 The United States Of America As Represented By The Department Of Energy Electrochemical thinning of silicon
US5306659A (en) * 1993-03-29 1994-04-26 International Business Machines Corporation Reach-through isolation etching method for silicon-on-insulator devices
US6110833A (en) 1998-03-03 2000-08-29 Advanced Micro Devices, Inc. Elimination of oxynitride (ONO) etch residue and polysilicon stringers through isolation of floating gates on adjacent bitlines by polysilicon oxidation
US5597738A (en) * 1993-12-03 1997-01-28 Kulite Semiconductor Products, Inc. Method for forming isolated CMOS structures on SOI structures
JPH0864674A (ja) * 1994-08-04 1996-03-08 Lg Semicon Co Ltd 半導体素子の絶縁方法
US5583368A (en) * 1994-08-11 1996-12-10 International Business Machines Corporation Stacked devices
DE19501838A1 (de) * 1995-01-21 1996-07-25 Telefunken Microelectron Verfahren zum Herstellen von SOI-Strukturen
JPH11195775A (ja) * 1997-12-26 1999-07-21 Sony Corp 半導体基板および薄膜半導体素子およびそれらの製造方法ならびに陽極化成装置
US5939750A (en) 1998-01-21 1999-08-17 Advanced Micro Devices Use of implanted ions to reduce oxide-nitride-oxide (ONO) etch residue and polystringers
US6030868A (en) * 1998-03-03 2000-02-29 Advanced Micro Devices, Inc. Elimination of oxynitride (ONO) etch residue and polysilicon stringers through isolation of floating gates on adjacent bitlines by polysilicon oxidation
US6043120A (en) * 1998-03-03 2000-03-28 Advanced Micro Devices, Inc. Elimination of oxynitride (ONO) etch residue and polysilicon stringers through isolation of floating gates on adjacent bitlines by polysilicon oxidation
US6051451A (en) * 1998-04-21 2000-04-18 Advanced Micro Devices, Inc. Heavy ion implant process to eliminate polystringers in high density type flash memory devices
JP3827056B2 (ja) 1999-03-17 2006-09-27 キヤノンマーケティングジャパン株式会社 層間絶縁膜の形成方法及び半導体装置
JP4304879B2 (ja) * 2001-04-06 2009-07-29 信越半導体株式会社 水素イオンまたは希ガスイオンの注入量の決定方法
US20040048437A1 (en) * 2002-09-11 2004-03-11 Dubin Valery M. Method of making oxide embedded transistor structures
GB0229212D0 (en) * 2002-12-14 2003-01-22 Koninkl Philips Electronics Nv Method of manufacture of a trench semiconductor device
WO2004073043A2 (en) * 2003-02-13 2004-08-26 Massachusetts Institute Of Technology Semiconductor-on-insulator article and method of making same
US7125458B2 (en) * 2003-09-12 2006-10-24 International Business Machines Corporation Formation of a silicon germanium-on-insulator structure by oxidation of a buried porous silicon layer
DE10345990B4 (de) * 2003-10-02 2008-08-14 Infineon Technologies Ag Verfahren zum Erzeugen einer Oxidschicht
JP2005229062A (ja) * 2004-02-16 2005-08-25 Canon Inc Soi基板及びその製造方法
US7172930B2 (en) * 2004-07-02 2007-02-06 International Business Machines Corporation Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer
FR2887370B1 (fr) * 2005-06-17 2007-12-28 Commissariat Energie Atomique Procede de fabrication d'un transistor isole a canal contraint
KR20120106893A (ko) * 2006-01-31 2012-09-26 엠이엠씨 일렉트로닉 머티리얼즈, 인크. 고 열 전도율을 가진 반도체 웨이퍼
US7541277B1 (en) 2008-04-30 2009-06-02 International Business Machines Corporation Stress relaxation, selective nitride phase removal
US8652929B2 (en) * 2011-12-23 2014-02-18 Peking University CMOS device for reducing charge sharing effect and fabrication method thereof
CN103390575A (zh) * 2013-08-01 2013-11-13 上海集成电路研发中心有限公司 一种全隔离结构的制作方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3575740A (en) * 1967-06-08 1971-04-20 Ibm Method of fabricating planar dielectric isolated integrated circuits
US3640806A (en) * 1970-01-05 1972-02-08 Nippon Telegraph & Telephone Semiconductor device and method of producing the same
JPS48102988A (es) * 1972-04-07 1973-12-24
US3966577A (en) * 1973-08-27 1976-06-29 Trw Inc. Dielectrically isolated semiconductor devices
JPS5246797B2 (es) * 1974-01-29 1977-11-28
US3919060A (en) * 1974-06-14 1975-11-11 Ibm Method of fabricating semiconductor device embodying dielectric isolation
JPS5146083A (en) * 1974-10-18 1976-04-20 Hitachi Ltd Handotaisochino seizohoho
US3954523A (en) * 1975-04-14 1976-05-04 International Business Machines Corporation Process for fabricating devices having dielectric isolation utilizing anodic treatment and selective oxidation
US3972754A (en) * 1975-05-30 1976-08-03 Ibm Corporation Method for forming dielectric isolation in integrated circuits
JPS5814507B2 (ja) * 1975-07-09 1983-03-19 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション シリコンを選択的にイオン食刻する方法

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GB1544393A (en) 1979-04-19
FR2382096A1 (fr) 1978-09-22
ES466901A1 (es) 1978-10-01
JPS53105988A (en) 1978-09-14
IT7820142A0 (it) 1978-02-10
NL7802011A (nl) 1978-08-28
BR7801029A (pt) 1979-01-02
FR2382096B1 (es) 1980-03-07

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