RU2795501C1 - Device for tolerance control of steady frequency deviation - Google Patents

Abstract

FIELD: electrical engineering.

SUBSTANCE: means for functional diagnostics of electrical assemblies (EA) with internal combustion engines, used as part of systems for diagnosing the technical condition of mobile power stations to assess the steady frequency deviation. The device contains a synchronous generator 1, the shaft of which is driven by an internal combustion engine (ICE) 2, equipped with a speed controller (SC). The output terminals of the generator 1 are connected to the input of the speed sensor 3 with a digital output, and through the power sensor 4 with a digital output to the load 5. The device also includes a multivibrator 6, a logical element NOT 7, a logical element AND 8, a reversible counter 9, the first 10, the second 11, the third 12 and the fourth 13 memory registers, the first 14, the second 15, the third 16, the fourth 17 and the fifth 18 numerical comparators, the setter 19 of the code of the norm of the steady frequency deviation, the first 20, the second 21, the third 22 and the fourth 23 short pulse shapers, the first 24 and the second 25 RS-triggers, the first 26 and the second 27 electronic keys, the power selector 28, the bus 29 INSTALLATION, high level signal bus 30, subtractor 31 and delay element 32.

EFFECT: expansion of functionality due to continuous monitoring of the steady frequency deviation and determination of compliance with regulatory requirements.

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Description

The invention relates to the field of electrical engineering, namely to the means of functional diagnostics of electrical units (EA) with internal combustion engines and can be used as part of systems for diagnosing the technical condition of mobile power stations to assess the steady frequency deviation.

Known methods for assessing the quality of electrical energy by frequency, including the steady frequency deviation by bench tests /1, 2/.

The disadvantage of these methods is the presence of a human factor, a low degree of automation and the need for load devices for their implementation.

The closest in technical essence to the invention is a frequency deviation meter from a given value containing a bus of the signal under study, a pulse shaper, a pulse generator, two AND logic elements, an RS flip-flop, a reversible counter, a master, a memory register, two NOT logic elements, the first, the second and a third short pulse shaper, the output of which is connected to the reset input of the RS flip-flop, two logical OR elements, a pulse distributor and a setup bus /3/.

This device gives an estimate of the frequency deviation from the set value in steady state and transient mode, without distinguishing between them. However, it does not determine whether the steady frequency deviation complies with the requirements of the standard.

The purpose of the invention is the expansion of functionality.

The purpose of the invention is achieved by the fact that the tolerance control device for a steady frequency deviation, containing a logic element AND, the first RS flip-flop, a reversible counter, the first setter, the first memory register, the NOT logic element, the first, second and third short pulse shaper, the output of which is connected to reset input of the first RS flip-flop, CHARACTERIZED in that, in order to expand the functionality, it is equipped with the second, third and fourth memory registers, the second RS flip-flop, the first, second, third, fourth and fifth numerical comparator, the fourth short pulse shaper, the first and a second electronic key, a second setter, a multivibrator, a subtractor, a delay element and an active power sensor with a digital output connected in series between the load and the generator driven by an internal combustion engine, to the tires of which the input of a frequency sensor with a digital output is connected, the discharges of which are connected to the corresponding bits of the inputs of the third and fourth memory registers, the second inputs of the second and third numerical comparator, the LESS output of which is connected to the input of the fourth short pulse shaper, connected by the output to the single input of the first RS flip-flop and the reset input of the fourth memory register, and the bits of the first input of the third comparator are connected with the corresponding bits of the output of the fourth memory register, the output of the second electronic key and the second input of the subtractor, the output bits of which are connected to the corresponding bits of the first input of the fourth numerical comparator, and the bits of the first input c are the bits of the first input of the second numerical comparator and the output of the third memory register, reset input which is connected to the output of the third generator of short pulses, and the input of the record is connected to the output of the first generator of short impulses, connected by the input to the LESS output of the second numerical comparator, in addition, the bits of the output of the first generator are connected to the corresponding bits of the second input of the fourth numerical comparator, the output of which is GREATER connected to the second input of the AND logic element, connected by the output to the single input of the second RS flip-flop, the reset input of which is connected to the INSTALLATION bus and the summing input of the reversible counter, connected by the borrow output to the first input of the AND logic element, and by the subtractive input - to the output of the second short pulse shaper, to the input of which the output GREAT and LESS of the first numerical comparator is connected, connected by the digits of the first input with the corresponding digits of the output of the first memory register, the output is EQUAL with the input of the third short pulse shaper and the control input of the first electronic key, and the corresponding digits of the second input are connected with the corresponding digits of the output the second memory register, the recording input of which is connected to the output of the logic element NOT, connected by the input to the output of the multivibrator and the recording input of the first memory register, the input bits of which are associated with the corresponding output bits of the power sensor, with the input bits of the second memory register and the input bits of the first electronic key, connected by bits of the output with the corresponding bits of the second input of the fifth numerical comparator, the bits of the first input of which are connected to the corresponding bits of the output of the second master, and the output is EQUAL through the delay element to the third input of the AND logic element, in addition, the bits of the input of the second electronic key are connected to the high-level bus , and its control input is connected to the inverse output of the first trigger.

The power sensor, the second memory register, the multivibrator, the logical NOT element, the first numerical comparator and their connections provide fixation of the moment of transition of the generating set to the steady state. The second master, the first electronic key, the fifth numerical comparator, the delay element and their connections fix the given load stage. The third memory register, the second numerical comparator and their connections are involved in the formation of the highest frequency code. The fourth memory register, the third numerical comparator, the second electronic key, the fourth short pulse shaper and their connections are involved in the formation of the code of the lowest frequency. The subtractor and its connections determine the code of the steady frequency deviation. The fourth comparator and its connections determines the compliance of the steady frequency deviation with the requirements of the standard.

In FIG. 1 shows a diagram of the device, Fig. 2 - regulatory characteristic of the electric unit.

The device contains a synchronous generator 1 (Fig. 1), the shaft of which is driven by an internal combustion engine (ICE) 2, equipped with a speed controller (RFV). The output terminals of the generator 1 are connected to the input of the speed sensor 3 with a digital output, and through the power sensor 4 with a digital output to the load 5. In addition, the device includes: multivibrator 6, NOT logic element 7, AND logic element 8, reversible counter 9, the first 10, the second 11, the third 12 and the fourth 13 memory registers, the first 14, the second 15, the third 16, the fourth 17 and the fifth 18 numerical comparators, the setter 19 of the code of the steady frequency deviation norm, the first 20, the second 21, the third 22 and the fourth 23 short pulse shapers, the first 24 and second 25 RS flip-flops, the first 26 and second 27 electronic keys, the power generator 28, the INSTALLATION bus 29, the high-level signal bus 30, the subtractor 31 and the delay element 32.

In the first setter 19, the code of the permissible frequency instability is entered, corresponding to 2δf _y , where δf _y is the steady frequency deviation (Fig. 2)

2δf _y =(f _max -f _min )/(2f _nom );

f _max - the highest frequency during the observation at a given level of load P _i ; f _min - the lowest frequency during the observation at a given load step P _i .

In the second master 28 is entered the code corresponding to the specified load stage P _i .

The device works as follows. By applying a signal to the bus 29 INSTALLATION, the circuit is brought to its initial state, in which the RS-flip-flop 25 is set to zero, and a unit is written to the reversible counter 9.

After excitation of generator 1, a harmonic voltage appears at its output terminals, which is fed to the input of sensor 3, at the output of which a frequency code appears. At the output of the power sensor 4, a code is generated corresponding to the load power 5. An impulse from the output of the multivibrator 6, this power code is entered into the memory register 10 and fed to the first input of the comparator 14. If the power increases, then the code at the first input of the comparator 14 is greater than the code at the second input, therefore, a signal appears at the output MORE than the comparator 14. On its front, the short pulse shaper 21 sends a pulse to the subtractive input of the counter 9, and a zero code is set at its output.

When the signal disappears at the output of the multivibrator 6, a signal appears at the output of the logic element NOT 7, which is fed to the write input of the memory register 11. The next power code from the output of the sensor 4 is written to the register 11, which is fed to the second input of the comparator 14. If this code turns out to be more than the previous power code recorded in register 10, then the signal at the first output of the comparator 14 disappears at the same time and a signal appears at the output LESS. At the input of the shaper 21 changes do not occur.

The comparator 14 constantly compares the previous and subsequent load power codes, which are recorded in memory registers 10 and 11. When a stationary load mode occurs, when equal codes are received at the inputs of the comparator 14 from registers 10 and 11, a signal appears at the output EQUAL to the comparator 14, which opens key 26.

Frequency deviation is measured at a fixed load step. Its level is set by the setter 28, from the output of which the code of the given power level is fed to the first input of the comparator 18. The second input of the comparator 18, through the electronic key 26, receives the power code from the output of the sensor 4. If the load power is equal to the specified power, then a signal appears on the output is EQUAL to the comparator 18, which, acting through the delay element to the third input of the element AND 8, allows the signal to pass to the output of the device.

On the edge of the signal from the output of the comparator 14, the shaper 22 generates a pulse that resets the register 12, starting the process of generating the code of the highest frequency f _max . The zero code from the output of the register 12 is fed to the first input of the comparator 15, the second input of which receives the code of the current frequency from the output of the sensor 3. In this case, a signal appears at the output LESS than the comparator 15, along the front of which the shaper 20 sends a pulse to the write input of the register 12, in which is written a new frequency code from the output of the sensor 3. Then the process of rewriting the code in the register 12 is repeated, and at its output the code of the highest frequency f _max is formed in the time interval with a stationary load.

Simultaneously, the pulse from the output of the shaper 22 translates the RS-flip-flop 24 to the zero state. A signal appears at the inverse output of trigger 24, which briefly opens the electronic key 27. At the same time, through the key 27, a single code from the high-level bus 30 enters the first input of the comparator 16, the second input of the comparator receives a frequency code from the output of sensor 3, which is less than a single code , therefore, a signal appears at the output LESS than the comparator 16. On the front of this signal, the shaper 23 generates a pulse that changes the state of the trigger 24, and at its inverse output the signal disappears, turning off the key 27. Simultaneously, the signal from the output of the shaper 23 into the register 13 writes the code of the current value frequency from the output of the sensor 3, which is fed to the first input of the comparator 16, the second input of which receives the subsequent current frequency value. The comparator 16 compares the codes of the previous and subsequent frequencies. If the code of the previous frequency coming from the output of register 13 is greater than the code of the next frequency coming from the output of sensor 3, then a signal appears at the output LESS than comparator 16. On the edge of this signal, shaper 23 generates a pulse that writes the next frequency code to register 13. The overwriting process frequency code in register 13 lasts until the code of the lowest frequency is written. As a result, at the output of the register 13 is formed the code of the lowest frequency f _min for the time interval with a stationary load.

The code of the highest frequency f _max from the output of the register 12 is fed to the first input of the subtractor 31, the second input of which is fed from the output of the register 13 the code of the lowest frequency f _min . The frequency difference code (f _max - f _min ), corresponding to the frequency instability zone, is fed from the subtractor 31 output to the first input of the comparator 17, the second input of which receives the instability norm code from the output of the master 19.

If the frequency instability exceeds the norm, then there is a signal at the output MORE comparator 17, which logic element AND 8 is prepared for the second input.

When leaving the stationary load zone, the equality of the codes at the output of registers 10 and 11 is violated and a signal appears at the output of the MORE or LESS comparator 14, on the front of which the shaper 21 generates a pulse. Since the counter 9 has a zero code at the output, the pulse from the output of the shaper 21 passes to the output of the counter loan and enters the first input of the AND 8 element. At the third input of the AND 8 element, the signal is maintained by the delay element. Therefore, the element And 8 opens and the signal from its output translates the trigger 25 in a single state. A signal appears at the direct output of trigger 25, which indicates the need for work on setting up the RFV.

If the frequency instability does not exceed the norm, then there is no signal at the output of the comparator 17, the element And 8 is closed by the second input and the trigger 25 does not change its state at the moment of exit from the stationary load zone.

At the beginning of the next time interval with a stationary load, a pulse reappears at the output of shaper 22 and the measurement process is repeated.

Thus, the device continuously monitors the steady-state frequency deviation, determining compliance with regulatory requirements.

Information sources

1. Sugakov V.G., Khvatov O.S. Fundamentals of automatic control of output electrical parameters of autonomous sources of electrical energy. Part 1. Automatic regulation of the frequency of autonomous sources of electrical energy: Tutorial. Kstovo, NVVIKU, 2008.

2. Sugakov V.G., Khvatov O.S. Systems for automatic control of ship power plant parameters. Part 1. Automatic control of the frequency of ship sources of electrical energy. Textbook for students (cadets) of the specialty 180404. Nizhny Novgorod, Publishing house of FGOU "VGAVT", 2010.

3. Author's certificate of the USSR No. 1679404, class. G01R 23/00, 1991.

Claims (1)

A tolerance control device for a steady frequency deviation, containing an AND logic element, the first RS flip-flop, a reversible counter, the first setter, the first memory register, the NOT logic element, the first, second and third short pulse shaper, the output of which is connected to the reset input of the first RS flip-flop , characterized in that, in order to expand the functionality, it is equipped with a second, third and fourth memory register, a second RS flip-flop, the first, second, third, fourth and fifth numerical comparator, a fourth short pulse shaper, the first and second electronic key, the second setter , a multivibrator, a subtractor, a delay element and an active power sensor with a digital output connected in series between the load and the generator driven by an internal combustion engine, to the tires of which the input of a frequency sensor with a digital output is connected, the bits of which are connected to the corresponding bits of the inputs of the third and fourth registers memory, the second inputs of the second and third numerical comparator, the LESS output of which is connected to the input of the fourth short pulse shaper, connected by the output to the single input of the first RS flip-flop and the reset input of the fourth memory register, and the bits of the first input of the third comparator are connected to the corresponding bits of the output of the fourth register memory, the output of the second electronic key and the second input of the subtractor, the output bits of which are connected to the corresponding bits of the first input of the fourth numerical comparator, and the bits of the first input are connected to the bits of the first input of the second numerical comparator and the output of the third memory register, the reset input of which is connected to the output of the third shaper short pulses, and the recording input - to the output of the first short pulse shaper connected by the input to the LESS output of the second numerical comparator, in addition, the bits of the output of the first setter are connected to the corresponding bits of the second input of the fourth numerical comparator, the output of which is GREATER connected to the second input of the logic element AND connected with the output to the single input of the second RS-flip-flop, the reset input of which is connected to the INSTALLATION bus and the summing input of the reversible counter, connected by the loan output to the first input of the AND logic element, and by the subtractive input - to the output of the second short pulse shaper, to the input of which the output is connected GREATER and LESS of the first numerical comparator connected by the first input bits with the corresponding output bits of the first memory register, the output EQUAL to the input of the third short pulse shaper and the control input of the first electronic key, and the corresponding bits of the second input - with the corresponding bits of the output of the second memory register, input record of which is connected to the output of the logical element NOT connected by the input to the output of the multivibrator and the record input of the first memory register, the input bits of which are associated with the corresponding output bits of the power sensor, with the input bits of the second memory register and the input bits of the first electronic key connected by the output bits with the corresponding bits of the second input of the fifth numerical comparator, the bits of the first input of which are connected to the corresponding bits of the output of the second master, and the output EQUAL through the delay element to the third input of the AND logic element, in addition, the input bits of the second electronic key are connected to the high-level bus, and its control the input is connected to the inverted output of the first trigger.

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