RU2787747C2 - Device for prestart check of frequency recovery time - Google Patents

Abstract

FIELD: electrical engineering.

SUBSTANCE: invention relates to the field of electrical engineering, to means for functional diagnostics of electrical units with internal combustion engines. A device for prestart check of frequency recovery time contains generator 1, connection clips 2, scaling unit 3, diode 4, limiter-generator 5, first 6 and second 7 generators of short pulses, inverter 8, first 9, second 10, third 11, and fourth 12 logical elements AND, first 13, second 14, and third 15 pulse counters, first 16 and second 17 electronic keys, first 18, second 19, and third 20 memory registers, first 21, second 22, and third 23 number comparators, subtractor 24, first 25 and second 26 RS triggers, first 27 and second 28 setting registers, logical element OR 29, memory unit 30, indicator 31, START bus 32, stable frequency pulse generator 33, pulse splitter 34, three-phase active power sensor 35 with a digital output, and delay element 36.

EFFECT: expansion of functional capabilities, possibility, during operation of electrical units, of assessment of frequency recovery time with a fixed stage of load rise without stand tests.

1 cl, 4 dwg

Description

SUBSTANCE: invention relates to the field of electrical engineering, namely to means for functional diagnostics of electrical units with internal combustion engines and can be used as part of systems for diagnosing the technical condition of mobile power plants to estimate the frequency recovery time during load surge.

Known methods for assessing the quality of electrical energy in terms of frequency, including the frequency recovery time during load surge through bench tests /1, 2/.

These methods require special stands with loads and instruments.

Known devices for monitoring generators /3, 4/, which provide low reliability.

The closest in technical essence to the invention is a device for controlling generators when the load changes, containing a power switch, a diode, a limiter-shaper, generator connection terminals, from the first to the fifth inverters, from the first to the fifth AND logic element, from the first to the third RS flip-flops /5 /.

This device makes it possible to estimate the frequency recovery time in case of a load surge during bench tests of the generating set. Its disadvantage is the impossibility of control during the operation of the generating set.

The purpose of the invention is the expansion of functionality.

The purpose of the invention is achieved by the fact that the recovery time tolerance control device, containing the first to the fourth AND logic elements, the OR logic element, the first and second RS flip-flop, the direct output of which is connected to the indicator input, the generator with clamps, to the voltage of which the scaling unit is connected , the output of which is connected through a diode to the input of the limiter-shaper, connected by the output to the input of the inverter is equipped with the first and second short pulse shaper, the first second and third pulse counter, the first and second electronic keys, the first second and third memory register, the first, second and third a numerical comparator, a subtractor, the first and second master registers, a memory block, a START bus, a stable frequency pulse generator, a pulse divider, a delay element and a three-phase active power sensor with a digital output, which is connected in series to the generator terminals, and by bits of the information output - to the corresponding data input bits of the second memory register, the output bits of which are associated with the corresponding input bits of the address of the memory block, the information input of the third memory register and the input of the reduced subtractor, the subtracted input bits of which are connected to the corresponding output bits of the third memory register, and the output bits - with the corresponding bits of the first input of the second numerical comparator, the bits of the second input of which are connected to the corresponding bits of the output of the first master register, and the output EQUAL to the single input of the first RS flip-flop, the direct output of which is connected to the first input of the third AND logic element, the output of which is connected to the counting input of the third counter, the output bits of which are associated with the corresponding bits of the first input of the third numerical comparator, connected by the second input bits to the corresponding output bits of the second master register, and the MORE output - to the first input of the fourth logic element the AND, the output of which is connected to a single input of the second RS-flip-flop, and the second input is connected to the LESS than output of the first numerical comparator, the second input bits of which are connected to the corresponding output bits of the memory block, and the first input bits are connected to the corresponding output bits of the first memory register, bits of the information input of which are connected to the corresponding bits of the outputs of the first and second electronic key, the bits of the inputs of which are connected to the corresponding bits of the outputs of the first and second counter, respectively, the counting inputs of which are connected, respectively, to the outputs of the first and second logic element AND, the first inputs of which are connected to the output of the generator pulses of a stable frequency, the output of which is also connected to the second input of the third AND logic element and the input of the pulse divider, the output of which is connected to the write input of the third memory register and the input of the delay element, the output of which is connected to the write input of the second memory register, reset the input of which is connected to the reset inputs of the third memory register, the first and second RS-flip-flops, the third counter and the START bus, in addition, the output of the shaper limiter is connected to the second input of the first AND logic element and the input of the first short pulse shaper, the output of which is connected to the reset input of the first counter, the control input of the second electronic key and the second input of the logical element OR, the output of which is connected to the write input of the first memory register, and the first input is connected to the control input of the first electronic key, the reset input of the second counter and the output of the second short pulse shaper, connected by the input to the output inverter and the second input of the second logic element AND.

The first and second short pulse shapers, the first and second pulse counters, the first and second electronic switches, the stable frequency pulse generator, the first memory register and their connections provide measurement and fixation of the current value of the generator current frequency. The first master register sets the load surge change stage for which the recovery time is estimated. The three-phase active power sensor, the second and third memory registers, the subtractor, the pulse divider, the delay element and their connections periodically measure the load change. The second numerical comparator provides fixation of the fact of the occurrence of a given load change. The second master register sets the standard frequency recovery time at a given stage of load change. The third impulse counter measures the time from the moment the load was applied. The memory block gives the value of the standard steady-state frequency corresponding to the current load of the generator. The third numerical comparator detects the moment of expiration of the standard time of the transient process. The first numerical comparator compares the current frequency value with the standard steady-state frequency after the completion of the transient.

In FIG. 1 shows a diagram of the device for tolerance control of the frequency recovery time, in Fig. 2 - dependence of the frequency f _ei on the load P _i of the generator (regulatory characteristic of the generating set), in Fig. 3 - diagrams of signals on the main elements of the circuit with an unfavorable outcome of the control, 4 - diagrams of signals on the main elements of the circuit with a favorable outcome of the control.

The device diagram (Fig. 1) contains a generator 1, terminals for connecting 2, a scaling unit 3, a diode 4, a limiter-shaper 5, the first 6 and second 7 short pulse shapers, an inverter 8, the first 9, the second 10, the third 11 and the fourth 12 logic elements And, first 13, second 14 and third 15 pulse counters, first 16 and second 17 electronic keys, first 18, second 19 and third 20 memory registers, first 21, second 22 and third 23 numerical comparators, subtractor 24, first 25 and second 26 RS flip-flops, the first 27 and second 28 master registers, logical element OR 29, memory block 30, indicator 31, START bus 32, stable frequency pulse generator 33, pulse divider 34, three-phase active power sensor 35 with digital output and a delay element 36. The cells of the memory block 30 contain codes of the reference frequency f _ei depending on the power P _i of the generator load (Fig. 2) which correspond to the expression for the relative reference frequency f _ei ,

f ei \ _u003d f ₀ -λS-δ f _y , o.u.,

where f ₀ is the relative idle frequency of the generator, p.u.

f ₀ =f ^a ₀ /f _nom ;

f ^a ₀ - absolute frequency at idle speed of the generator, Hz;

f _nom - absolute rated frequency of the generator, Hz;

λ is the relative active power of the generator load, r.u.

λ=P _i /R _nom ;

P _i - current active power of the generator load, kW;

P _nom - rated active power of the generator load, kW;

S - slope (droop) of the regulatory characteristic of the electrical unit;

δ f _y - steady-state frequency deviation at constant load (permissible frequency instability) r.u.

The device works as follows. In register 27, the code of the controlled load step is entered (standard values are 25%, 50% or 100% of the rated power). In register 28, the code of the standard frequency recovery time for the accepted surge stage is written (depends on the accuracy class of the frequency controller). A signal is sent to the START bus 32, which resets the counter 15 and the memory registers 19 and 20, and the RS-flip-flops 25 and 26 are transferred to the state when there is no signal at the direct output.

From the moment of excitation of generator 1, voltage is present at terminals 2, which is applied to scaling unit 3. From scaling unit 3, through diode 4, a positive half-wave of generator 1 voltage is supplied to the input of limiter-shaper 5, and a pulse appears at the output of limiter-shaper 5, the duration of which equal to the half cycle of the generator voltage. This pulse prepares the element And 9 on the second input. On the counting input of the counter 13 through the first input of the element And 9 begin to receive pulses from the output of the pulse generator 33. At the output of the counter 13 is formed by the frequency code of the generator 1 for a positive half-wave.

When a negative half-wave voltage of the generator 1 appears, the signal at the output of the limiter-shaper 5 disappears, and a signal appears at the output of the inverter 8, which prepares the AND element 10 for the second input. On its edge of the pulse from the output of the inverter 8 short pulse shaper 7 generates a pulse. This pulse resets the counter 14 and briefly opens the key 16, which connects the output of the counter 13 to the input of the register 18. The same pulse from the output of the shaper 7 goes through the OR element 29 to the write input of the register 18, into which the current frequency code is written from the output of the counter 13. At the output of register 18, the code of the current frequency of generator 1 appears. At the same time, the formation of the next frequency code for a negative half-cycle begins. Through the first input of the element And 10, the pulses of the generator 33 enter the counting input of the counter 14, at the output of which the next frequency code is formed. Its formation is completed with the advent of the next positive voltage half-wave, when the signal reappears at the output of the limiter-shaper 5, which prepares the element And 9 on the second input. On the edge of the same signal, the short pulse shaper 6 generates a pulse that briefly opens the key 17 and the pulse through the OR element 29 writes the frequency code from the output of the counter 14 into the memory register 18. Further, the process of generating the frequency code of the generator 1 is repeated, and at the output of the memory register 18 the current frequency code is always present.

At the same time, the load change is analyzed according to the power code at the output of the sensor 35. After the appearance of a signal on the START bus 32, a zero code is present at the outputs of the memory registers 19 and 20. When the first pulse appears at the output of the divider 34, the zero code is written to the register 20, and the power code is written to the register 19 with a time delay specified by the delay element 36. With the second and subsequent pulses from the output of divider 34 to register 20, the power code is rewritten at the previous time from the output of register 19, and the power code at the current time from the output of sensor 35 is written to register 20. As a result, the code is constantly present at the output of register 20 power at the previous moment of time, which is fed to the input of the subtracted subtractor 24, and at the output of the register 19, the power code is constantly set at the next moment, which is fed to the input of the reduced subtractor 24. At the output of the subtractor 24, during the entire operation of the generating set, there is a code for the magnitude of the load power change , which is fed to the first input of the comparator 22.

If, during the operation of the generating set, the magnitude of the load change corresponds to the controlled one, then the code at the first input of the comparator 22 coincides with the code at the output of the master register 27 applied to the second input of the comparator 22. In this case, a signal appears at the output EQUAL to the comparator 22, which translates the RS-trigger 25 into a singular state. The signal from the direct output of the RS-flip-flop 25 prepares the element AND 11 on the first input and through it the counting input of the counter 15 begins to receive pulses from the output of the generator 33, forming at the output of the counter 15 the time code of the transient process, which is fed to the first input of the numerical comparator 23. When this time exceeds the standard time, the code of which is set at the output of the master 28 and applied to the second input of the comparator 23, the signal X23 (Fig. 3) appears at the output MORE of the comparator 23. This signal X23 prepares the AND element 12 for the first input. The address of the memory block 30 receives the code of the current power value and at its output the code X30 of the standard frequency corresponding to this power, taking into account the slope of the regulatory characteristic and the permissible frequency instability, which is fed to the second input of the numerical comparator 21. If the current frequency, the code X18 of which filed from the output of the register 18 to the first input of the comparator 21, less than the X30 code of the standard frequency, a signal appears at the output LESS than the comparator 21, which passes through the AND element 12 and puts the RS-flip-flop 26 into a single state. The X26 signal from the direct output of the RS-flip-flop 26 is fed to the indicator 31, which indicates the need for adjustment of the frequency controller.

If the frequency recovery time t _B is less than the standard time t _BE (Fig. 4), then by the time the signal X23 appears at the output of the numerical comparator 23, the signal X21 at the output of the numerical comparator 21 disappears, closing the AND element 12 on the second input, preventing a change in the state of the RS flip-flop 26. Indicator 31 does not indicate the need to adjust the frequency regulator.

Thus, the device allows in the process of operation of the generating set to estimate the frequency recovery time at a fixed stage of load surge without bench tests.

Sources of information

1. Sugakov V.G., Khvatov O.S. Fundamentals of automatic control of output electrical parameters of autonomous sources of electrical energy. Part 1. Automatic regulation of the frequency of autonomous sources of electrical energy: Tutorial. Kstovo, NVVIKU, 2008.

2. Sugakov V.G., Khvatov O.S. Systems for automatic control of ship power plant parameters. Part 1. Automatic control of the frequency of ship sources of electrical energy. Textbook for students (cadets) of the specialty 180404. Nizhny Novgorod, Publishing house of FGOU "VGAVT", 2010.

3. Author's certificate of the USSR No. 632022, class. H02N 3/44, 1977.

4. Author's certificate of the USSR No. 1260885, class. G01R 31/34, 1985.

5. Device for monitoring generators when the load changes. Description of the invention to the author's certificate SU 1484101, class. G 01 R 31/34, 1987.

Claims (1)

Frequency recovery time tolerance control device, containing from the first to the fourth AND logic elements, the OR logic element, the first and second RS flip-flop, the direct output of which is connected to the indicator input, the generator with clamps, the voltage of which is connected to the scaling unit, the output of which is through the diode connected to the input of the limiter-shaper, connected with the output to the input of the inverter, characterized in that, in order to expand the functionality, it is equipped with the first and second short pulse shaper, the first second and third pulse counter, the first and second electronic keys, the first second and third memory register, first, second and third numerical comparator, subtractor, first and second master register, memory block, START bus, stable frequency pulse generator, pulse divider, delay element and three-phase active power sensor with digital output, which is connected in series to the generator terminals, and by discharges information output - to the corresponding bits of the information input of the second memory register, the output bits of which are associated with the corresponding bits of the input of the address of the memory block, the information input of the third memory register and the input of the reduced subtractor, the input bits of the subtracted which are connected to the corresponding bits of the output of the third memory register, and the output bits - with the corresponding bits of the first input of the second numerical comparator, the bits of the second input of which are connected to the corresponding bits of the output of the first master register, and the output EQUAL to the single input of the first RS flip-flop, the direct output of which is connected to the first input of the third logic element AND, the output of which is connected to the counting input of the third counter, the output bits of which are connected with the corresponding bits of the first input of the third numerical comparator, connected by the bits of the second input to the corresponding bits of the output of the second master register, and the output MORE - to the lane to the left input of the fourth logic element AND, the output of which is connected to a single input of the second RS-flip-flop, and the second input is connected to the output LESS than the first numerical comparator, the bits of the second input of which are associated with the corresponding bits of the output of the memory block, and the bits of the first input are connected with the corresponding bits of the output of the first memory register, the bits of the information input of which are connected to the corresponding bits of the outputs of the first and second electronic key, the bits of the inputs of which are connected to the corresponding bits of the outputs of the first and second counters, respectively, the counting inputs of which are connected, respectively, to the outputs of the first and second logic element AND, the first inputs of which connected to the output of the stable frequency pulse generator, the output of which is also connected to the second input of the third logic element AND and the input of the pulse divider, the output of which is connected to the write input of the third memory register and the input of the delay element, the output of which is connected to the input of the writing the second memory register, the reset input of which is connected to the reset inputs of the third memory register, the first and second RS flip-flops, the third counter and the START bus, in addition, the output of the shaper limiter is connected to the second input of the first AND logic element and the input of the first short pulse shaper, the output which is connected to the reset input of the first counter, the control input of the second electronic key and the second input of the OR logic element, the output of which is connected to the write input of the first memory register, and the first input is connected to the control input of the first electronic key, the reset input of the second counter and the output of the second short generator pulses connected by the input to the output of the inverter and the second input of the second logic element AND.

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