RU2643155C1 - Voltage quality corrector - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: device comprises booster transformers (1-1, 1-2 and 1-3), phase blocks (2-1, 2-2 and 2-3) of transformer control in each phase, each of which has the first single-phase half-wave rectifier (3), the second single-phase bridge rectifier (4), the first (5) and the second (6) limiter-driver, a totalizer (7), a short pulse shaper (8), an analog-to-digital converter (ADC) (9), a delay element (10), an exclusive-OR gate (11), a NOT gate (12), the first (13), the second (14), the third (15) and the fourth (16) electronic keys which form a switch (17), a digital-to-analog converter (DAC) (18), a three-dimensional memory unit (19), a subtracter (20). In each control unit (2-1, 2-2 and 2-3), the output bits of the memory register (21) are connected to the input bits of the third coordinate of the memory unit (19), the corresponding output bits of the master register (22) - to the input bits of the second coordinate, and the output of the fixed frequency pulse generator (23) - to the inverting inputs of the totalizer (7). Phase loads (24-1, 24-2 and 24-3) are connected in series with the secondary windings of the corresponding transformers (1-1, 1-2 and 1-3). The corresponding phases of the three-phase AC generator (26) with an excitation control system (27) are connected to the network terminals (25-0, 25-1, 25-2 and 25-3).

EFFECT: device simultaneously provides compensation for distortion of the AC voltage curve and imbalance of phase voltages.

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Description

The invention relates to electrical engineering and can be used to control the voltage of three-phase alternators of autonomous sources of electrical energy.

Known systems for controlling the excitation and voltage correctors of alternators / 1, 2 /.

The disadvantage of these devices is the impossibility of maintaining a sinusoidal shape of the voltage curve when working on a non-linear load, which causes higher harmonic components, and a satisfactory unbalance coefficient of phase voltages when working on a variable inhomogeneous asymmetric load, since the excitation is controlled for the generator as a whole, and not for individual phases.

A known phase-voltage unbalance corrector, comprising three phase voltage meters, variators built on resistors included in each phase, and a control circuit / 3 /.

The disadvantage of the corrector is the loss of energy on the variator resistors and the inability to correct the shape of the voltage curve.

The closest in technical essence to the invention is a voltage curve shape correction device comprising an alternating voltage generator with an excitation control system, the circuit of which includes a variable non-linear load and a secondary winding of a boost transformer, the primary winding of which is connected to the output of the switch formed from the first to the eighth electronic switches, the first and second rectifiers, the inputs of which are connected to the load terminals, and the output of the second rectifier the substitute is directly connected to the input of the second ADC and through the low-pass filter to the input of the first ADC, the output bits of which are connected to the corresponding bits of the information input of the third memory register and the first input of the numerical comparator, the output of the second ADC connected to the input of the subtracted subtractor, the information output of which is connected to the input of the DAC, and the input of the decremented one is connected to the output of the memory block, the input of the first coordinate of which is connected with the output of the summing counter and the input of the second memory register, the input is a swarm of coordinates - with the output of the second memory register, and an input of the third coordinate - with the output of the first memory register, the input of which is connected to the output of the third memory register and the second input of the numerical comparator, the output of which is MORE through the third short pulse generator is connected to the recording input of the third memory register, the dump input of which is connected to the dump input of the totalizing counter connected by the count input to the output of the stable pulse generator and the output of the delay element, the input of which is connected to the recording inputs and the first and second memory registers and the output of the OR element, the first input of which is connected through the first shaper to the output of the limiter connected to the input of the HE element, the output of which is connected through the second shaper of the short pulses to the second input of the OR element and the RS- a trigger, a single input of which is connected to the output of the first shaper of short pulses, a direct output to the control electrodes of the fifth and sixth electronic keys, and an inverse output to the control electro I will give the seventh and eighth electronic keys, while the output of the latter is combined with the output of the fifth electronic key and connected to the first terminal of the transformer primary winding, the second terminal of which is connected to the outputs of the sixth and seventh electronic keys, the input of the last of which is combined with the input of the fifth electronic key and connected to the combined output of the first and third electronic keys, with the inputs of the third and second electronic keys connected to the DAC output, the inputs of the first and fourth electronic keys to the MAC terminal A, and the control electrodes of the first and second electronic keys are connected to the output of the sign of the positive difference of the subtractor, the output of the signs of the negative difference of which is connected to the control electrodes of the third and fourth keys, in addition, the outputs of the second and fourth electronic keys are combined and connected to the inputs of the sixth and eighth electronic keys /four/.

The disadvantage of this device is the inability to maintain a satisfactory coefficient of unbalance of phase voltages when working on a variable inhomogeneous asymmetric load.

The purpose of the invention is the expansion of functionality.

The purpose of the invention is achieved in that a voltage quality corrector comprising a three-phase alternating voltage generator with an excitation control system, in phases of which a variable non-uniform non-linear load and secondary windings of boost boost transformers are connected in series, the primary windings of which are connected to the outputs of the switch of the corresponding phase control unit, each of which In addition, it has: a short-pulse shaper, a logic element NOT, the first and second rectifiers, inputs to which are connected to the corresponding phases of the load, with the output of the first rectifier connected to the input of the first limiter-driver, and the output of the second rectifier connected to the input of the ADC, the output bits of which are connected to the corresponding bits of the input of the subtracted subtractor, connected by the bits of the output to the corresponding bits of the input of the DAC, and the input the reduced subtractor is connected to the output of the memory block, the input of the first coordinate of which is with the output of the summing counter, the counting input of which is connected to the output of the pulse generator s of stable frequency, and the dump input - with the output of the delay element, is equipped with a memory register that sets the register, and in each phase control unit - an exclusive OR logic element and a second limiting driver, to the input of which the output of the second rectifier is connected, and the output through the former is short pulses connected to the input of the delay element, and the output of the first limiter-driver is connected to the first input of the logic element exclusive OR connected by the second input with the output of the sign of positive p of the subtractor, and the output is directly from the control inputs of the first and fourth electronic keys of the switch and through the logic element NOT to the control inputs of the second and third electronic keys of the switch, one output pole of which is formed by the combined outputs of the first and second electronic keys, and the second pole of the third and the fourth electronic key, while the inputs of the first and third electronic keys of the switch are connected to the DAC output, and the inputs of the second and fourth keys are connected to the MASS terminal, while The input output second coordinates of the memory blocks of the phase control units are combined and connected to the corresponding output register bits, and the counting inputs of the totalizing phase control units are also combined and connected to the output of the stable frequency pulse generator, in addition, the corresponding output bits of the first totalizing counter of the control unit the phases are connected to the corresponding bits of the input of the memory register, the recording input of which is connected to the output of the short-pulse shaper of the block systematic way of the first phase and the corresponding output bits - with the corresponding input bits of the third register memory location of the phase control units.

The master register and its connections provide the same levels of all phase voltages. The second limiter-shaper of the phase control units and its connections organize the measurement of frequency. The exclusive OR gate and its connections provide the choice of the moment of switching electronic keys and determine the polarity of the voltage boost. Connecting the inputs of the memory register to the control unit of the first phase, and the output of the register to the inputs of the third coordinate of the memory blocks of all phases provides an early update of the half-cycle code in two phases, which increases accuracy and reduces the consumption of the element base, which increases reliability.

In FIG. 1 is a diagram of a voltage quality corrector; FIG. 2 - diagrams of signals on the main elements of the circuit.

The voltage quality corrector circuit (Fig. 1) contains in each phase boost boost transformers 1-1, 1-2 and 1-3, phase transformer control blocks 2-1, 2-2 and 2-3, each of which has a first rectifier 3 single-phase half-wave, second rectifier 4 single-phase bridge, first 5 and second 6 limiter-shaper, totalizing counter 7, shaper 8 short pulses, analog-to-digital converter (ADC) 9, delay element 10, exclusive logic element OR 11, logic element NOT 12 , first 13, second 14, third 15 and fourth 16th electronic keys that form the switch 17, digital-to-analog converter (DAC) 18, three-dimensional memory block 19, subtractor 20, memory register 21. In each control unit 2-1, 2-2 and 2-3 to the input bits of the second coordinate of the block the memory is connected to the corresponding bits of the output of the master register 22, and to the counting inputs of the counter 7 - the output of the generator 23 pulses of a stable frequency. Phase loads 24-1, 24-2 and 24-3 are connected in series with the secondary windings of the respective transformers 1-1,1-2 and 1-3. The corresponding phases of the three-phase alternating current generator 26 with the excitation control system 27 are connected to the network terminals 25-0, 25-1, 25-2 and 25-3.

The scheme works as follows. At the output of the master register 22, a code K _{Um of} amplitude U _{m of a} given voltage is set, which is fed to the input of the second address of the memory register 19 and is connected with the amplitude U _{m by the} expression

where ΔU ₉ is the quantization step of the ADC 9.

When the positive half-wave voltage u (t) (Fig. 2) appears on the load 24-1 of the first phase, it is supplied to the measuring input of the first control unit 2-1, and passes through the rectifier 3, entering the input of the limiter-former 5. At the output of the limiter -shaper 5 a rectangular pulse X5 appears, the duration of which is equal to half-cycle with a positive half-wave of voltage u (t) at load 24-1 and voltage u _C (t) on source buses 25. This pulse X5 is supplied to the first input of the element 11 exclusive OR.

, которое поступает на вход АЦП 9. На выходе АЦП 9 появляется код K_U и мгновенного напряжения u(t), который поступает на вход В (вычитаемого) вычитателя 20. Код K_U и связан с напряжением u(t) выражениемAt the same time, the voltage u (t) from the load 24-1 is supplied to the input of the second rectifier 4, and a pulsating voltage appears at its output

which goes to the input of the ADC 9. At the output of the ADC 9 appears the code K _U and the instantaneous voltage u (t), which goes to the input B of the (subtracted) subtractor 20. Code K _U and is connected with the voltage u (t) by the expression

In addition, the voltage from the output of the rectifier 4 is supplied to the input of the shaper-limiter 6, the output of which appears a pulse with a duration equal to the half-cycle voltage u (t). On the front of this pulse, the shaper 8 generates a short pulse passing through the delay element 10 to the discharge input of the counter 7, which is reset. The counting input of the counter 7 receives pulses of a stable frequency from the output of the generator 23. At the output of the counter 7 appears the code K _{t of the} current time t, which is associated with the code K _t expression

where T _E - the pulse repetition period from the output of the generator 23.

The current time code K _t is input to the first address (current time address) of the memory unit 19. At the end of the half-period with the arrival of the next half-wave of voltage u (t) by the pulse from the output of the shaper 8, the code K _{T of the} half-period of voltage u (t) is written to the register 21, which is associated with the period T of the voltage u (t) by the expression

From the output of the register 21, the code K _{T of the} half-period of voltage u (t) is fed to the input of the third address (period address) of the memory block 19.

In the cells of the memory unit 19, the codes K _{UC of the} instantaneous values of the reference voltage u _e (t) with a perfectly sinusoidal shape are associated, which are related by the expression

Where

Depending on the current time, amplitude and voltage period u (t), the corresponding code K _{UC of the} reference voltage appears at the output of the memory unit 19, which is fed to the input A (of the decreasing) subtractor 20. At the output of the subtractor 20, the instantaneous difference or deviation code K _D appears load voltage values from the reference voltage

This CD code goes to the input of the DAC 18, and a voltage appears at its output

where ΔU ₁₈ is the quantization step of the DAC 18

K _VD - transformation ratio boost booster transformer 1

U _D - voltage on the secondary winding of the transformer 1.

The instantaneous voltage value u ₁₈ (t) from the output of the DAC 18 is supplied to the switch 17, built on electronic switches 13 ... 16 and which sets the direction of voltage correction by changing the polarity of the voltage u ₁₈ (t), as follows.

If the voltage u (t) has positive instantaneous values (positive half-wave, time interval t ₁ -t ₆ , Fig. 2), the signal from the output of the driver 5 is fed to the first input of the element exclusive OR 11, and if the instantaneous values of u (t) less than the instantaneous values of the reference voltage u _E (t), when there is a signal X20 ⁽¹⁾ at the output of the sign of the positive difference of the subtractor 20 (time interval t ₁ -t ₂ , Fig. 2), then the signal X11 at the output of the element exclusive OR 11 is absent. Therefore, the signal X12 appears at the output of the element HE 12, which is supplied to the control electrodes of the keys 14 and 15, opening them. Through the public keys 14 and 15, the primary winding of the transformer 1-1 is supplied with voltage from the output of the DAC 18 in direct polarity. As a result, the secondary winding 1-1 of the transformer appears voltage u _A (t), which is added to the load voltage u (t), and the instantaneous value of the mains voltage u _C (t) is increasing, approaching the reference voltage, and _E (t). Similarly, the process proceeds at time intervals t ₃ -t ₄ and t ₅ -t ₆ (Fig. 2).

If, with positive instantaneous values of voltage u (t), it turns out to be more than instantaneous values of the reference voltage u _e (t), when there is no signal X20 ⁽¹⁾ at the output of the positive difference sign of subtractor 20 (time interval t ₂ -t ₃ , Fig. 2) , the signal X11 appears at the output of the element exclusive OR 11, and the signal at the output of the element NOT 12 disappears. In this case, the electronic keys 13 and 16 are turned on, and the voltage from the output of the DAC 18 with reverse polarity is supplied to the primary winding of the transformer 1-1. The voltage u _D (t) appears on the secondary winding of the transformer 1-1, which is subtracted from the voltage u (t), maintaining the instantaneous value of the mains voltage u _C (t) at the level of the reference voltage u _e (t). On the time interval t ₄ -t ₅ (Fig. 2), the corrector works similarly.

(фиг. 2).If the voltage u (t) has negative instantaneous values (negative half-wave, time interval t ₆ -t ₁₁ , Fig. 2), there is no signal at the output of the driver 5, which is supplied to the first input of the element exclusive OR 11. When the instantaneous voltage value u (t) deviates to a smaller modulo (time interval t ₆ -t ₇ , Fig. 2) relative to the reference voltage u (t), the code K _UC at the first input A of the subtractor 20 is larger than the code K _U on its second input B, therefore, there is a signal X20 ⁽¹⁾ at the output of the sign of the positive difference of the subtractor 20. This signal X20 ^{(1) is} supplied to the second input of the exclusive OR 11 element, at the output of which the signal X11 appears, by which the electronic keys 13 and 16 are opened. Through open keys 13 and 16, the voltage from the output of the DAC 18 is supplied to the primary transformer 1-1. In this case, the voltage u _D (t) appears on the secondary winding of the transformer 1-1, which coincides in phase with the voltage u (t), which leads to the correction of the voltage curve u _C (t) in the direction of increase in absolute value. The process proceeds similarly at time intervals t ₈ -t ₉ and t ₁₀ -t ₁₁ (Fig. 2). If, at negative instantaneous voltage values u (t), it deviates upward in magnitude from the reference one (time interval t ₇ -t ₈ , Fig. 2), then signal X20 ^{(1) is} absent at the output of the sign of positive difference 20. Therefore, the signal at the output of the element exclusive OR 11 is absent, but the signal X12 appears at the output of the element NOT 12, which opens the keys 14 and 15. From the output of the DAC 18, the voltage is supplied through the keys 14 and 15, which ensures a decrease in the modulus of the instantaneous voltage values u _C ( t) up to the reference voltage. The process proceeds similarly on a time interval

(Fig. 2).

As a result, at any time on the secondary winding of the transformer 1-1, a voltage u _D (t) appears, which corrects the instantaneous value of the mains voltage u _C (t), bringing its shape closer to the ideal sinusoid u _Э (t)

Similarly, the voltage curve is corrected in other phases, while boost boost transformers 1-2 and 1-3 work respectively with control units 2-2 and 2-3. Moreover, in all three phases the voltage amplitudes are equal and correspond to the level specified by the register 22.

Thus, there is an expansion of functionality due to the simultaneous approximation of the shape of the voltage curve to the ideal sinusoid and to eliminate the imbalance of phase voltages.

The error of the correction of the voltage curve depends on the capacity of N digital elements included in the device circuit. At N = 10, the error does not exceed 0.001.

Coefficient K _palates unbalance of phase voltages depends on the quantization step ΔU 9 ADC ₁₈ and DAC 18

where U _max is the largest phase voltage;

U _min is the smallest phase voltage;

U _nom - rated phase voltage.

When N = 10 K coefficient _palates unbalance does not exceed 0.001.

Information sources

1. Sugakov V.G. Systems for automatic regulation of electrical energy parameters of ship power plants. Part 2. Automatic voltage regulation of ship sources of electric energy: textbook. Allowance. / V.G. Sugakov, O.S. Grabs. - N. Novgorod: Publishing House of FSEI HPE "VGAVT", 2011.180 s.

2. Patent for invention No. 25233005 according to the application 2013108756 of 02.27.2013, class. H02P 9/14.

3. Patent for invention No. 2580941 according to the application 2014152161/07 of 12.22.2014, class. H02P 9/14.

4. Patent for invention No. 2580944 according to the application 2014143243/07 dated 10.27.2014, class. H02P 9/14.

Claims (1)

A voltage quality corrector comprising a three-phase alternating voltage generator with an excitation control system, the phases of which consistently include a non-uniform non-linear load and secondary windings of boost transformers, the primary windings of which are connected to the outputs of the switch of the corresponding phase control unit, each of which, in addition, has: short pulse shaper, logic element NOT, first and second rectifiers, the inputs of which are connected to the corresponding load, and the output of the first rectifier is connected to the input of the first limiter-shaper, and the output of the second rectifier is connected to the input of the ADC, the output bits of which are connected to the corresponding bits of the input of the subtracted subtractor, connected by the bits of the output to the corresponding bits of the input of the DAC, and the input of the reduced subtractor is connected to the output of the memory block, the input of the first coordinate of which is the output of the summing counter, the counting input of which is connected to the output of the stable-frequency pulse generator, and the reset input d - with the output of the delay element, characterized in that with the aim of expanding the functionality it is equipped with a memory register that sets the register, and in each phase control unit - an exclusive OR element and a second driver, to the input of which the output of the second rectifier is connected, and the output through a shaper of short pulses connected to the input of the delay element, and the output of the first limiter-former is connected to the first input of the logic element exclusive OR, connected by the second input to the output of the sign of the positive difference of the subtractor, and the output directly with the control inputs of the first and fourth electronic switch keys and through the logic element NOT with the control inputs of the second and third electronic switch keys, one output pole of which is formed by the combined outputs of the first and second electronic keys, and the second the pole of the third and fourth electronic keys, while the inputs of the first and third electronic keys of the switch are connected to the DAC output, and the inputs of the second and fourth keys are connected to the MASSA terminal, while the corresponding input bits of the second coordinate of the memory blocks of the phase control units are combined and connected to the corresponding bits of the output of the master register, and the counting inputs of the summing counters of the phase control units are also combined and connected to the output of the stable frequency pulse generator, in addition, the corresponding output bits the summing counter of the control unit of the first phase is connected to the corresponding bits of the input of the memory register, the recording input of which is connected to the output of the short pulses of the control unit of the first phase, and the corresponding output bits with the corresponding input bits of the third coordinate of the memory register of the control blocks of all phases.

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