RU2631862C1 - Voltage corrector - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: device citrcuit comprises booster transformers (1-1, 1-2 and 1-3), phase blocks (2-1, 2-2 and 2-3) of transformer control in each phase, each of which has the first single-phase half-wave rectifier (3), the second single-phase bridge rectifier (4), the first (5) and the second (6) limiter-driver, a memory register (7), a short pulse shaper (8), an analog-to-digital converter (ADC) (9), a delay element (10), an exclusive-OR gate (11), a NOT gate (12), the first (13), the second (14), the third (15) and the fourth (16) electronic keys which form a switch (17), a digital-to-analog converter (DAC) (18), a three-dimensional memory unit (19), a subtracter (20), a totalizer (21). In each control unit (2-1, 2-2 and 2-3), the corresponding output bits of the master register (22) are connected to the input bits of the second coordinate of the memory unit, and the output of the fixed frequency pulse generator (23) - to the inverting inputs of the totalizer (21). Phase loads (24-1, 24-2 and 24-3) are connected in series with the secondary windings of the corresponding transformers (1-1, 1-2 and 1-3). The corresponding phases of the three-phase AC generator (26) with an excitation control system (27) are connected to the network terminals (25-0, 25-1, 25-2 and 25-3). The device simultaneously provides compensation for distortion of the AC voltage curve and imbalance of phase voltages.

EFFECT: expanded operating capabilities.

2 dwg

Description

The invention relates to electrical engineering and can be used to control the voltage of three-phase alternators of autonomous sources of electrical energy.

Known systems for controlling the excitation and voltage correctors of alternators / 1, 2 /.

The disadvantage of these devices is the impossibility of maintaining a sinusoidal shape of the voltage curve when working on a non-linear load, which causes higher harmonic components, and a satisfactory unbalance coefficient of phase voltages when working on a variable inhomogeneous asymmetric load, since the excitation is controlled for the generator as a whole, and not for individual phases.

A known phase-voltage unbalance corrector, comprising three phase voltage meters, variators built on resistors included in each phase, and a control circuit / 3 /.

The disadvantage of the corrector is the loss of energy on the variator resistors and the inability to correct the shape of the voltage curve.

The closest in technical essence to the invention is a voltage curve shape correction device comprising an alternating voltage generator with an excitation control system, in the circuit of which a variable non-linear load and a secondary winding of a boost transformer are connected in series, the primary winding of which is connected to the output of the switch formed from the first to eighth electronic keys, the first and second rectifiers whose inputs are connected to the load terminals, and the output of the second rectifier The meter is directly connected to the input of the second ADC and through the low-pass filter to the input of the first ADC, the output bits of which are connected to the corresponding bits of the information input of the third memory register and the first input of the numerical comparator, the output of the second ADC connected to the input of the subtracted subtractor, the information output of which is connected to the input of the DAC, and the input of the diminished one is connected to the output of the memory block, the input of the first coordinate of which is connected with the output of the summing counter and the input of the second memory register, the input is second the second coordinate is with the output of the second memory register, and the input of the third coordinate is with the output of the first memory register, the input of which is connected to the output of the third memory register and the second input of the numerical comparator, the output of MORE through the third short pulse generator is connected to the recording input of the third memory register, the dump input of which is connected to the dump input of the totalizing counter connected by the count input to the output of the stable pulse generator and the output of the delay element, the input of which is connected to the recording inputs the first and second memory registers and the output of the OR element, the first input of which is connected through the first driver of the short pulses to the output of the driver-limiter connected to the input of the element NOT, the output of which through the second driver of the short pulses is connected to the second input of the OR element and the reset input of the RS-trigger , the single input of which is connected to the output of the first shaper of short pulses, the direct output to the control electrodes of the fifth and sixth electronic keys, and the inverse output to the control electrodes I will give the seventh and eighth electronic keys, while the output of the latter is combined with the output of the fifth electronic key and connected to the first terminal of the transformer primary winding, the second terminal of which is connected to the outputs of the sixth and seventh electronic keys, the input of the last of which is combined with the input of the fifth electronic key and connected to the combined output of the first and third electronic keys, with the inputs of the third and second electronic keys connected to the DAC output, the inputs of the first and fourth electronic keys to the MAC terminal A, and the control electrodes of the first and second electronic keys are connected to the output of the sign of the positive difference of the subtractor, the output of the signs of the negative difference of which is connected to the control electrodes of the third and fourth keys, in addition, the outputs of the second and fourth electronic keys are combined and connected to the inputs of the sixth and eighth electronic keys /four/.

The disadvantage of this device is the inability to maintain a satisfactory coefficient of unbalance of phase voltages when working on a variable inhomogeneous asymmetric load.

The purpose of the invention is the expansion of functionality.

The purpose of the invention is achieved by the fact that the corrector contains a three-phase alternating voltage generator with an excitation control system, in phases of which a variable non-uniform non-linear load and secondary windings of the boost transformer are connected in series, the primary windings of which are connected to the outputs of the switch of the corresponding phase control unit, each of which, moreover, has: a short-pulse shaper, a logic element NOT, the first and second rectifiers, the inputs of which are connected to the corresponding phases of the load, the output of the first rectifier connected to the input of the first limiter-shaper, and the output of the second rectifier connected to the input of the ADC, the output bits of which are connected to the corresponding bits of the input of the subtracted subtractor, connected by the bits of the output to the corresponding bits of the input of the DAC, and the input of the reduced subtractor is connected with the output of the memory block, the input of the third coordinate of which is connected with the output of the memory register, and the input of the first coordinate of which is with the output of the summing counter, the counting input it is connected to the output of a stable-frequency pulse generator, and the discharge input - with the output of the delay element, is equipped with a master register and in each phase control unit a logic element exclusive OR and a second limiter-former, to the input of which the output of the second rectifier is connected, and the output through the former is short pulses connected to the input of the delay element and the input of the memory register record, and the output of the first limiter-driver is connected to the first input of the logic element exclusive OR, with associated with the second input with the output of the sign of the positive difference of the subtractor, and the output directly with the control inputs of the first and fourth electronic switch keys and through the logic element NOT with the control inputs of the second and third electronic switch keys, one output pole of which is formed by the combined outputs of the first and second electronic key, and the second pole - the third and fourth electronic keys, while the inputs of the first and third electronic keys of the switch are connected to the output of the DAC, and the inputs of the WTO The fourth and fourth keys are connected to the MASS terminal, in addition, the corresponding input bits of the second coordinate of the memory blocks of the phase control units are combined and connected to the corresponding output bits of the master register, and the counting inputs of the summing counters of the phase control units are also combined and connected to the output of a stable frequency pulse generator.

The master register and its connections provide the same levels of all phase voltages. The second limiter-shaper of the phase control units and its connections organize the measurement of frequency. The exclusive OR gate and its connections provide the choice of the moment of switching electronic keys and determine the polarity of the voltage boost.

In FIG. 1 is a diagram of a voltage corrector; FIG. 2 - diagrams of signals on the main elements of the circuit.

The voltage corrector circuit (Fig. 1) contains in each phase additional boost transformers 1-1, 1-2 and 1-3, phase transformer control units 2-1, 2-2 and 2-3, each of which has a first rectifier 3 single-phase single-half-wave, second rectifier 4 single-phase bridge, first 5 and second 6 limiter-shaper, memory register 7, shaper 8 short pulses, analog-to-digital converter (ADC) 9, delay element 10, exclusive logic element OR 11, logical element NOT 12, first 13, second 14, third 15 and fourth 16 electronically the keys that form the switch 17, a digital-to-analog converter (DAC) 18, a three-dimensional memory block 19, a subtractor 20, a totalizing counter 21. In each control unit 2-1, 2-2 and 2-3 to the input bits of the second coordinate of the block the corresponding output bits of the master register 22 are connected to the memory, and the output of the generator 23 of stable frequency pulses is connected to the counting inputs of the counter 21. Phase loads 24-1, 24-2 and 24-3 are connected in series with the secondary windings of the respective transformers 1-1, 1-2 and 1-3. The corresponding phases of the three-phase alternating current generator 26 with the excitation control system 27 are connected to the network terminals 25-0, 25-1, 25-2 and 25-3.

The scheme works as follows. At the output of the master register 22, a code K _{Um of} amplitude U _{m of a} given voltage is set, which is fed to the input of the second address of the memory register 19 and is connected with the amplitude U _{m by the} expression

where ΔU ₉ is the quantization step of the ADC 9.

When the positive half-wave voltage u (t) (Fig. 2) appears on the load 24-1 of the first phase, it is supplied to the measuring input of the first control unit 2-1, and passes through the rectifier 3, entering the input of the limiter-former 5. At the output of the limiter -shaper 5 a rectangular pulse X5 appears, the duration of which is equal to half-cycle with a positive half-wave of voltage u (t) at load 24-1 and voltage u _C (t) on source buses 25. This pulse X5 is supplied to the first input of the element 11 exclusive OR.

, которое поступает на вход АЦП 9. На выходе АЦП 9 появляется код K_U мгновенного напряжения u(t), который поступает на вход В (вычитаемого) вычитателя 20. Код K_U связан с напряжением u(t) выражениемAt the same time, the voltage u (t) from the load 24-1 is supplied to the input of the second rectifier 4, and a pulsating voltage appears at its output

which goes to the input of the ADC 9. At the output of the ADC 9 appears the code K _{U of the} instantaneous voltage u (t), which goes to the input B of the (subtracted) subtractor 20. The code K _U is connected to the voltage u (t) by the expression

In addition, the voltage from the output of the rectifier 4 is supplied to the input of the shaper-limiter 6, the output of which appears a pulse with a duration equal to a half-period of voltage u (t). On the front of this pulse, the shaper 8 generates a short pulse passing through the delay element 10 to the discharge input of the counter 21, which is reset. The counting input of the counter 21 receives stable frequency pulses from the output of the generator 23. At the output of the counter 21, the code K _{t of the} current time t appears, which is associated with the code K _{t by the} expression

where T _E - the pulse repetition period from the output of the generator 23.

The current time code K _t is input to the first address (current time address) of the memory unit 19. At the end of the half-cycle with the arrival of the next half-wave of voltage u (t) by the pulse from the output of the shaper 8, code K _{T of the} half-period of voltage u (t) is written to the register 7, which is associated with the period T of the voltage u (t) by the expression

From the output of register 7, the code K _{T of the} half-period of voltage u (t) is fed to the input of the third address (period address) of the memory unit 19.

In the cells of the memory unit 19, the codes K _{UC of the} instantaneous values of the reference voltage u _e (t) with a perfectly sinusoidal shape are associated, which are related by

Where

Depending on the current time, amplitude and voltage period u (t), the corresponding code K _{UC of the} reference voltage appears at the output of the memory unit 19, which is fed to the input A (of the reduced) subtractor 20.

At the output of the subtractor 20, a code K _{D of the} difference or deviation of the instantaneous value of the load voltage from the reference voltage appears

This code K _{D is} fed to the input of the DAC 18, and a voltage appears at its output

where ΔU ₁₈ is the quantization step of the DAC 18

K _VD - transformation ratio boost booster transformer 1

U _D - voltage on the secondary winding of the transformer 1.

The instantaneous voltage value u ₁₈ (t) from the output of the DAC 18 is supplied to the switch 17, built on electronic switches 13 ... 16 and which sets the direction of voltage correction by changing the polarity of the voltage u ₁₈ (t), as follows.

If the voltage u (t) has positive instantaneous values (positive half-wave (time interval t ₁ -t ₆ , in Fig. 2), the signal from the output of the driver 5 is fed to the first input of the element exclusive OR 11, and if the instantaneous values of u (t ) is less than the instantaneous values of the reference voltage u _E (t), when there is a signal X20 ⁽¹⁾ at the output of the sign of the positive difference of the subtractor 20 (time interval t ₁ -t ₂ , Fig. 2), then the signal X11 at the output of the element exclusive OR 11 is absent Therefore, the signal X12 appears at the output of the element NOT 12, which arrives at the control electrodes of the keys 14 and 15. Opening the keys through the open keys 14 and 15, the voltage from the output of the DAC 18 in direct polarity is applied to the primary winding of the transformer 1-1. As a result, the voltage u _Д appears on the secondary winding of the transformer 1-1 ), which is added to the voltage at the load u (t), and the instantaneous value of the mains voltage u _С (t) increases as it approaches the reference voltage u _Э (t). Similarly, the process proceeds at time intervals t ₃ -t ₄ and t ₅ -t ₆ (Fig. 2).

If for positive instantaneous voltage values u (t), it turns out to be more than instantaneous values of the reference voltage u _e (t) when there is no signal X20 ⁽¹⁾ at the output of the positive difference sign of subtractor 20 (time interval t ₂ -t ₃ , Fig. 2 ), an X11 signal appears at the output of the element exclusive OR 11, and the signal at the output of the element NOT 12 disappears. In this case, the electronic keys 13 and 16 are turned on, and the voltage from the output of the DAC 18 with reverse polarity is supplied to the primary winding of the transformer 1-1. The voltage u _D (t) appears on the secondary winding of the transformer 1-1, which is subtracted from the voltage u (t), maintaining the instantaneous value of the mains voltage u _C (t) at the level of the reference voltage u _e (t). On the time interval t ₄ -t ₅ (Fig. 2), the corrector works similarly.

If the voltage u (t) has negative instantaneous values (negative half-wave, time interval t ₆ -t ₁₁ , Fig. 2), there is no signal at the output of the driver 5, which is supplied to the first input of the element exclusive OR 11. When the instantaneous voltage value u (t) deviates in a smaller direction in absolute value (time interval t ₆ -t _{7 of} Fig. 2) relative to the reference voltage u (t), the code K _UC at the first input A of the subtractor 17 is larger than the code K _U at its second input B, therefore, there is a signal X20 ⁽¹⁾ at the output of the sign of the positive difference of the subtractor 20. This signal X20 ^{(1) is} supplied to the second input of the exclusive OR element 11, at the output of which the signal X11 appears which opens the electronic keys 13 and 16. Through the public keys 13 and 16 voltage from the output of the DAC 18 is supplied to the primary ku transformer 1-1. In this case, the voltage u _d (t) appears on the secondary winding of the transformer 1-1, which coincides in phase with the voltage u (t), which leads to the correction of the voltage curve u _C (t) in the direction of increase in absolute value. The process proceeds similarly at time intervals t ₈ -t ₉ and t ₁₀ -t ₁₁ (Fig. 2). If, at negative instantaneous voltage values u (t), it deviates upward from the reference modulo (time interval t ₇ -t ₈ , Fig. 2), then the signal X20 ⁽¹⁾ at the output of the positive difference sign 20 is absent. Therefore, the signal at the output of the element exclusive OR 11 is absent, but the signal X12 appears at the output of the element NOT 12, which opens the keys 14 and 15. From the output of the DAC 18, the voltage is supplied through the keys 14 and 15, which ensures a decrease in the modulus of the instantaneous voltage values u _C ( t) up to the reference voltage. Similarly, the process proceeds on the time interval t ₉ -t ₁₀ (Fig. 2).

As a result, at any time on the secondary winding of the transformer 1-1, a voltage u _D (t) appears, which corrects the instantaneous value of the mains voltage u _C (t), bringing its shape closer to the ideal sinusoid u _Э (t)

Similarly, the voltage curve is corrected in other phases, while boost boost transformers 1-2 and 1-3 work respectively with control units 2-2 and 2-3. Moreover, in all three phases the voltage amplitudes are equal and correspond to the level specified by the register 22.

Thus, there is an expansion of functionality due to the simultaneous approximation of the shape of the voltage curve to the ideal sinusoid and to eliminate the imbalance of phase voltages.

The error of the correction of the voltage curve depends on the capacity of N digital elements included in the device circuit. At N = 10, the error does not exceed 0.001.

Coefficient K _palates unbalance of phase voltages depends on the quantization step ΔU 9 ADC ₁₈ and DAC 18

where U _max is the largest phase voltage;

U _min is the smallest phase voltage;

U _nom - rated phase voltage.

When N = 10 K coefficient _palates unbalance does not exceed 0.001.

Information sources

1. Sugakov V.G. Systems for automatic regulation of electrical energy parameters of ship power plants. Part 2. Automatic voltage regulation of ship sources of electric energy: textbook. allowance / V.G. Sugakov, O.S. Grabs. - N. Novgorod: Publishing House of FSEI HPE "VGAVT", 2011.180 s.

2. Patent for invention No. 25233005 according to the application 2013108756 of 02.27.2013, class. Н02Р 9/14.

3. Patent for invention No. 2580941 according to the application 2014152161/07 of 12.22.2014, class. Н02Р 9/14.

4. Patent for invention No. 2580944 according to the application 2014143243/07 dated 10.27.2014, class. Н02Р 9/14.

Claims (1)

A voltage corrector comprising a three-phase alternating voltage generator with an excitation control system, in phases of which a variable non-uniform non-linear load and secondary windings of boost transformers are connected in series, the primary windings of which are connected to the switch outputs of the corresponding phase control unit, each of which also has: short pulses, logic element NOT, the first and second rectifiers, the inputs of which are connected to the corresponding phases of the load the output of the first rectifier is connected to the input of the first limiter-shaper, and the output of the second rectifier is connected to the ADC input, the output bits of which are connected to the corresponding bits of the input of the subtracted subtractor, connected by the bits of the output to the corresponding bits of the input of the DAC, and the input of the reduced subtractor is connected to the output a memory block, the input of the third coordinate of which is connected with the output of the memory register, and the input of the first coordinate of which is with the output of a summing counter, the counting input of which is connected to the output to the pulse generator of a stable frequency, and the dump input - with the output of the delay element, characterized in that for the purpose of expanding the functionality it is equipped with a master register, and in each phase control unit the logic element excludes OR and the second limiter-former, to the input of which the output of the second rectifier, and the output through the shaper of short pulses is connected to the input of the delay element and the input of the memory register, the output of the first limiter-shaper connected to the first an exclusive OR gate connected to the input of the second input with the output of the sign of the positive difference of the subtractor, and the output directly to the control inputs of the first and fourth electronic switch keys and through the logical element NOT to the control inputs of the second and third electronic switch keys, one output pole of which is formed the combined outputs of the first and second electronic keys, and the second pole of the third and fourth electronic keys, while the inputs of the first and third electronic keys to the mutators are connected to the output of the DAC, and the inputs of the second and fourth keys are connected to the MASSA terminal, in addition, the corresponding bits of the input of the second coordinate of the memory blocks of the phase control units are combined and connected to the corresponding bits of the output of the master register, and the counting inputs of the summing counters of the phase control units are also combined and connected to the output of a stable frequency pulse generator.

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