RU2793860C1 - Device for tolerance control of transient frequency deviation - Google Patents

Abstract

FIELD: electrical engineering.

SUBSTANCE: means for functional diagnostics of electrical units with internal combustion engines, part of systems for diagnosing the technical condition of mobile power stations for assessing transient frequency deviation during load surge. A device for tolerance control of transient frequency deviation is proposed, consisting of a generator 1, clamps for connecting 2, a starting element 3, a diode 4, a limiter-shaper 5, an inverter 6, a short pulse shaper 7, the first 8 and second 9 delay elements, the first 10, second 11 and third 12 logical elements I, first 13, second 14 and third 15 memory registers, first 16 and second 17 subtractors, first 18, second 19 and third 20 numerical comparators, first 21 and second 22 master registers, memory block 23, stable frequency pulse generator 24, pulse divider 25, pulse counter 26, RS trigger 27, indicator 28, START bus 29, three-phase active power sensor 30 with digital output, first 31 and second 32 logic elements OR, electronic switch 33, second shaper 34 of short pulses and the second RS-trigger 35.

EFFECT: increasing the efficiency of the assessment.

1 cl, 4 dwg

Description

SUBSTANCE: invention relates to the field of electrical engineering, namely to means for functional diagnostics of electrical units (EA) with internal combustion engines, and can be used as part of systems for diagnosing the technical condition of mobile power stations for assessing transient frequency deviation during load surge.

Known methods for assessing the quality of electrical energy by frequency, including transient frequency deviation during load surge through bench tests /1, 2/.

The disadvantage of these methods is the presence of a human factor, a low degree of automation and the need for load devices for their implementation.

The closest in technical essence to the invention is a device for monitoring generators when the load changes, including a starting element, a diode, a limiter-shaper, a stable frequency pulse generator, the first and second AND logic elements, a NOT logic element, a pulse counter, a delay element, the first and second RS flip-flops, the first and second comparator blocks, the OR logic element, the indication block, the "Reset" button, the waiting multivibrator, the differentiator, and the comparator blocks contain two numerical comparators and a setter.

The disadvantage of this device is the presence of a human factor, a low degree of automation, the need to take the EA out of operation and the need for load devices for bench tests.

The purpose of the invention is to increase the efficiency of the assessment.

The purpose of the invention is achieved by the fact that the tolerance control device for transient frequency deviation, containing the first and second numerical comparators to the second input bits of which the corresponding bits of the outputs of the first and second master registers, respectively, are connected, the START bus associated with the reset inputs of the second and first RS flip-flop is direct the output of which is connected to the input of the indicator, the starting element connected to the terminals of the generator, to the output of which the input of the limiter-shaper is connected through a diode, the output of which is connected to the second input of the first logic element AND, connected by the first input to the output of the pulse generator of a stable frequency, and the output - with the counting input of the pulse counter, in addition, the output of the limiter-shaper is connected to the input of the inverter connected by the output to the input of the short pulse shaper, the output of which is connected to the input of the first delay element and the first input of the second logic element , the second and third memory registers, the first and second subtractors, a three-phase active power sensor with a digital output, a memory unit, a second delay element and a second short pulse shaper, a pulse divider, an electronic key, a second OR logic element, a third AND logic element, and the third numerical comparator, the GREATER output of which is connected to the second input of the second logic element AND, the output LESS - to the second input of the third logic element AND, the output of which is connected to the single input of the first RS flip-flop, the first input to the output of the first short pulse shaper, the third input - to the output GREATER of the second numerical comparator, and the fourth input - to the single input of the second RS flip-flop and the output EQUAL to the first numerical comparator, the bits of the first input of which are connected to the corresponding bits of the output of the first subtractor, the bits of the second input of which are connected to the corresponding bits of the output of the third memory register , and the corresponding bits of the first input - with the corresponding bits of the input of the third memory register, the input of the address of the memory block and the output of the second memory register, the input bits of which are connected to the corresponding bits of the output of a three-phase active power sensor with a digital output connected in series to the generator circuit, and the record input is connected to the output of the second delay element, the input of which is connected to the output of the pulse divider connected by the input to the output of the pulse generator of a stable frequency, and the write input of the third memory register, the reset input of which is connected to the START bus, the reset input of the first and second memory registers and the first input of the second logical OR element connected by the second input to the output of the first delay element, and the output - to the reset input of the pulse counter, the output bits of which are associated with the corresponding bits of the input of the first memory register, with - the corresponding bits of the second input of the third numerical comparator and the corresponding bits of the output of the electronic key connected bits of the input to the high-level bus, and the control input to the output of the second short pulse shaper, the input of which is connected by the direct output of the second RS flip-flop and the third input of the first logic element AND, in addition, the output of the second short pulse shaper is connected to the second input of the first logic element OR , the first input of which is connected to the output of the second logic element AND, and the output - to the write input of the first memory register, the output bits of which are associated with the corresponding bits of the first input of the third numerical comparator and the bits of the first input of the second subtractor, the output bits of which are connected to the corresponding bits of the first input the second numerical comparator, and the bits of the second input - to the corresponding bits of the output of the memory block.

The third and second memory registers, a three-phase active power sensor with a digital output, a pulse divider, the first comparator and the first master register, the second delay and coupling element provide control of the load change and establish the fact of the specified load step surge. The pulse counter, the first memory register, the first and second OR logic elements, the second RS flip-flop, the second short pulse shaper, the electronic key and the third numerical comparator and their connections provide the measurement of the minimum frequency during the transient. The second subtractor and its connections calculates the transient frequency deviation when a given load is applied. The second numerical comparator, the second master register, the third logical element And and their connections provide fixation of the fact of the output of the transient frequency deviation beyond the limits of the zone of permissible values.

In FIG. 1 shows a diagram of a device for tolerance control of transient frequency deviation, in Fig. 2 - dependence of the frequency f _ei on the load P _i of the generator (regulatory characteristic of the generating set), in Fig. 3 - diagrams of signals on the main elements of the circuit with an unfavorable outcome of the control, 4 - diagrams of signals on the main elements of the circuit with a favorable outcome of the control.

The device diagram (Fig. 1) contains a generator 1, terminals for connecting 2, a starting element 3, a diode 4, a limiter-shaper 5, an inverter 6, a short pulse shaper 7, the first 8 and second 9 delay elements, the first 10, the second 11 and third 12 logic elements And, first 13, second 14 and third 15 memory registers, first 16 and second 17 subtractors, first 18, second 19 and third 20 numerical comparators, first 21 and second 22 master registers, memory block 23, pulse generator 24 stable frequency, divider 25 pulses, pulse counter 26, RS-trigger 27, indicator 28, bus START 29, three-phase active power sensor 30 with digital output, first 31 and second 32 OR logic elements, electronic key 33, second shaper 34 short pulses and a second RS flip-flop 35.

The cells of the memory block 23 contain the codes of the reference frequency f _yct depending on the power P _i of the generator load (Fig. 2) which correspond to the expression for the relative reference frequency f _ei ,

f _yct -f ₀ - λS, oe,

where f ₀ is the relative idle frequency of the generator, p.u.

f ₀ \u003d f ^a ₀ / f _nom ,

f ₀ - absolute frequency at idle speed of the generator, Hz;

f _nom - absolute rated frequency of the generator, Hz;

λ is the relative active power of the generator load, r.u.

λ= P _i / R _nom .

P _i - current active power of the generator load, kW;

P _nom - rated active power of the generator load, kW;

S - slope (droop) of the regulatory characteristic of the electrical unit;

The device works as follows. In register 21, the code of the controlled load step is entered (standard values are 25%, 50% or 100% of the rated power). In register 22, the code of the standard value of the transient frequency deviation X22 for the accepted surge stage is written (depends on the accuracy class of the frequency controller). A signal is sent to the START bus 29, which resets the memory registers 13, 14, 15 and the counter 26, and the RS-flip-flops 27 and 35 are transferred to the state when there is no direct output signal.

The analysis of load changes is carried out according to the power code at the output of the sensor 30. After the appearance of a signal on the START bus 29, a zero code is present at the outputs of the memory registers 14 and 15. When the first pulse appears at the output of divider 25, a zero code is written to register 15, and the power code from the output of sensor 30 is written to register 14 with a time delay set by delay element 9. At the second and subsequent pulses from the output of divider 25, register 15 is rewritten the power code at the previous time from the output of register 14, and the power code at the current time from the output of sensor 30 is recorded in register 14. As a result, the power code at the previous time is constantly present at the output of register 15, which is fed to the second input of the subtractor 16, and at the output of the register 14, the power code is constantly set at the next moment of time, which is fed to the first input of the subtractor 16. At the output of the subtractor 16, during the entire operation of the generating set, there is a code for the magnitude of the load power change, which is fed to the first input of the comparator 18.

If, during the operation of the generating set, the magnitude of the load change corresponds to the controlled one, then the code at the first input of the comparator 18 coincides with the code at the output of the master register 21 applied to the second input of the comparator 18. In this case, a signal appears at the output EQUAL to the comparator 18, which prepares the logic element 12 according to the fourth input and the frequency control starts. When this RS-flip-flop 35 is transferred to a single state signal from the output of the comparator 18. The signal from the direct output of the RS-flip-flop 35 logic element And 10 is prepared by the third input. Simultaneously, on the edge of the signal from the direct output of the RS-trigger 35, the short pulse shaper 34 generates a pulse that briefly opens the electronic key 33, from the output of which a single code is written to the memory register 13 by a pulse passing through the logical element OR 31.

From the starting element 3 through the diode 4, a positive half-wave of the voltage of the generator 1 is supplied to the input of the limiter-shaper 5, and a pulse appears at the output of the limiter-shaper 5, the duration of which is equal to the half-cycle of the voltage of the generator 1. This pulse prepares the AND element 10 at the second input. Pulses from the output of the pulse generator 24 begin to flow to the counting input of the counter 26 through the first input of the AND element 10. At the output of the counter 26, the frequency code of the generator 1 is generated. therefore, a signal appears at the output MORE than the comparator 20, preparing the logic element AND 11 on the second input.

With the advent of the negative half-wave voltage of the generator 1, the signal at the output of the limiter-shaper 5 disappears, and appears at the output of the inverter 6. On the edge of this signal, the shaper 7 short pulses generates a pulse passing through the logic elements AND 11 and OR 31 to the write input of the memory register 13, in which the frequency code is written from the output of the counter 26. Then the counter 26 is reset by a pulse coming from the output of the delay element 8 , through the logical element OR 32 to the reset input, preparing the counter 26 for the next frequency measurement. With a load surge in the initial period, the frequency decreases (Figs. 3 and 4). Therefore, the next frequency code at the output of the counter 26 is less than the previous code recorded in the memory register 13. These codes are compared by the comparator 20, and a signal appears at its output MORE, allowing the rewriting of the new lower frequency value from the output of the counter 26 into the memory register 13. Process rewriting the frequency code in register 13 occurs until the moment the code of the minimum frequency f _min is written (Fig. 3 and 4), after which the frequency begins to increase and the generated frequency codes at the output of counter 26 are greater than the code written in register 13. A signal appears at the output LESS than the comparator 20, which prepares the AND gate 12 on the second input.

The power code from the output of the memory register 14 is fed to the address input of the memory block 23 and the code X23 of the steady frequency f _set appears at its output (Fig. 3 and 4) for a given load of the generator 1, which is fed to the second input of the subtractor 17. At the first input of the subtractor 17 code XI3 of the minimum frequency f _min (Fig. 3 and 4) from the output of the register 13. At the output of the subtractor 17 appears the code X17 transient frequency deviation for a given load stage δf _lane =f _ycm -f _min . From the output of the subtractor 17, the code X17 is fed to the first input of the comparator 19, at the second input of which there is the code X22 of the allowable transient frequency deviation for a given load stage, coming from the output of the master register 22.

If the transient frequency deviation exceeds the allowable value (Fig. 3), then a signal appears at the output MORE comparator 19, which prepares the AND logic element 12 on the third input. When a negative half-wave of the generator 1 voltage appears, when a pulse occurs at the output of the short pulse shaper 7, a pulse passes through the AND 12 logic element to the single input of the RS flip-flop 27. A signal appears at the direct output of the RS flip-flop 27, which turns on the indicator 28, indicating the need to adjust the frequency controller.

If the transient frequency deviation does not exceed the allowable value (Fig. 4), then the signal at the output MORE than the comparator 19 does not appear, maintaining the prohibition on opening the logic element AND 12 and turning on the indicator 28.

Thus, the device allows, during the operation of the electric unit, to evaluate the transient frequency deviation when a fixed load step is applied without bench tests.

Information sources

1. Sugakov V.G., Khvatov O.S. Fundamentals of automatic control of output electrical parameters of autonomous sources of electrical energy. Part 1. Automatic regulation of the frequency of autonomous sources of electrical energy: Tutorial. Kstovo, NVVIKU, 2008.

2. Sugakov V.G., Khvatov O.S. Systems for automatic control of ship power plant parameters. Part 1. Automatic control of the frequency of ship sources of electrical energy. Textbook for students (cadets) of the specialty 180404. Nizhny Novgorod, Publishing house of FGOU "VGAVT", 2010.

3. Author's certificate of the USSR No. 323962, class. G01R 23/00, 1991.

Claims (1)

Tolerance control device for transient frequency deviation, containing the first and second numerical comparators, to the second input bits of which the corresponding bits of the outputs of the first and second master registers, respectively, are connected, the START bus associated with the reset inputs of the second and first RS flip-flop, the direct output of which is connected to the input indicator, a starting element connected to the terminals of the generator, to the output of which the input of the limiter-shaper is connected through a diode, the output of which is connected to the second input of the first logic element AND, connected by the first input to the output of the stable frequency pulse generator, and the output to the counting input of the pulse counter , in addition, the output of the limiter-shaper is connected to the input of the inverter connected by the output to the input of the short pulse shaper, the output of which is connected to the input of the first delay element and the first input of the second logic element AND, characterized in that, in order to increase the efficiency of the assessment, it is equipped with the first, second and the third memory registers, the first and second subtractors, a three-phase active power sensor with a digital output, a memory unit, a second delay element and a second short pulse shaper, a pulse divider, an electronic key, a second OR logic element, a third AND logic element and a third numerical comparator, output MORE than which is connected to the second input of the second logic element AND, the output LESS - to the second input of the third logic element AND, the output of which is connected to the single input of the first RS-trigger, the first input - to the output of the first short pulse shaper, the third input - to the output GREATER of the second numerical comparator, and the fourth input - to a single input of the second RS flip-flop and the output EQUAL to the first numerical comparator, the first input bits of which are connected to the corresponding bits of the output of the first subtractor, the second input bits of which are connected to the corresponding output bits of the third memory register, and the corresponding bits of the first input - with the corresponding bits of the input of the third memory register, the input of the address of the memory block and the output of the second memory register, the input bits of which are connected to the corresponding bits of the output of a three-phase active power sensor with a digital output connected in series to the generator circuit, and the write input is connected to the output of the second delay element , the input of which is connected to the output of the pulse divider connected by the input to the output of the stable frequency pulse generator, and the write input of the third memory register, the reset input of which is connected to the START bus, the reset input of the first and second memory registers and the first input of the second OR logic element, connected by the second input with the output of the first delay element, and the output - with the reset input of the pulse counter, the output bits of which are associated with the corresponding bits of the input of the first memory register, with the corresponding bits of the second input of the third numerical comparator and the corresponding bits of the output of the electronic key connected by the input bits to the high-level bus , and the control input - to the output of the second short pulse shaper, the input of which is connected by the direct output of the second RS flip-flop and the third input of the first logic element AND, in addition, the output of the second short pulse shaper is connected to the second input of the first logic element OR, the first input of which is connected to the output of the second logic element AND, and the output - to the write input of the first memory register, the output bits of which are connected with the corresponding bits of the first input of the third numerical comparator and the bits of the first input of the second subtractor, the output bits of which are connected to the corresponding bits of the first input of the second numerical comparator, and the bits the second input - to the corresponding bits of the output of the memory block.

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