RU2766868C1 - Gallium arsenide buffer amplifier - Google Patents

Abstract

FIELD: analogue microelectronics.

SUBSTANCE: invention relates to analogue microelectronics and can be used as a gallium arsenide output stage of a power amplifier of various analogue devices, allowing operation in conditions of penetrating radiation, low and high temperatures. Gallium arsenide buffer amplifier comprises device input (1) and output (2), first (3) and second (5) input field-effect transistors with control p-n junction, reference current source (6), first (4) and second (7) power supply buses, potential matching circuit (10) and output p-n-p transistor (11). Reference current source (6) is made on additional field-effect transistor (8) with control p-n junction. Source through first (9) additional resistor and the gate of the additional field-effect transistor (8) are connected to second (7) power supply bus. Drain of the additional field-effect transistor (8) is the second output of the reference current source (6), is connected to the source of first (3) input field-effect transistor through a potential matching circuit (10) and is connected to the base of the output p-n-p transistor (11). Drains of first (3) and second (5) input field-effect transistors are matched with first (4) power supply bus. Gate of second (5) input field-effect transistor is connected to the gate of first (3) input field-effect transistor and input (1) of the device, and the source is connected to the emitter of the output p-n-p transistor (11) and output (2) of the device. First output of the reference current source (6) and the collector of the output p-n-p transistor (11) are matched with second (7) power supply bus.

EFFECT: design of a buffer amplifier implemented only on JFET gallium arsenide field-effect transistors with a control p-n junction and bipolar GaAs p-n-p transistors.

3 cl, 5 dwg

Description

The invention relates to the field of analog microelectronics and can be used as a gallium arsenide output stage of a power amplifier of various analog devices that can operate under conditions of penetrating radiation, low and high temperatures.

A significant number of circuits for output stages of power amplifiers and buffer amplifiers (BU) of analog microelectronic products are known, which are implemented on bipolar (BJT) and field-effect (JFet, CMOS, SOI, SOS, etc.) transistors, as well as when they are connected together [1- 26]. In many applications, the CU scheme is adapted to specific technological processes and external influencing factors, for example, the influence of low temperatures and radiation, since only in this case is the implementation of the limiting parameters of the control unit ensured.

Currently, in Russian and foreign microelectronics, increased attention is paid to gallium arsenide microcircuits. This direction of creating an electronic component base is one of the most promising in the tasks of space instrumentation. However, the features of gallium arsenide technological processes impose significant restrictions on the types of implemented transistors and their characteristics. So, for example, the gallium arsenide technological process, mastered by US firms [27-30], as well as the Minsk Research Institute of Radio Materials (https://mniirm.by/), is focused on the manufacture of analog circuits containing only GaAs field-effect transistors with control pn junction and bipolar GaAs pnp transistors. The use of other semiconductor devices is not allowed. This imposes significant restrictions on the circuitry of analog devices oriented to a given technological process.

The closest prototype (Fig. 1) of the claimed device is a buffer amplifier presented in RF patent No. 2710917, 2019. It contains (Fig. 1) input 1 and output 2 of the device, the first 3 input field-effect transistor with a control pn junction, the drain of which is matched with the first 4 power supply bus, the second 5 input field effect transistor with a control pn junction, the gate of which is connected to the gate of the first 3 input field effect transistor with a control pn junction and input 1 of the device, the drain is matched with the first 4 power supply bus, and the source is connected to the output 2 devices, a reference current source 6, the first output of which is matched with the second 7 bus of the power supply.

A significant drawback of the prototype buffer amplifier is that it cannot be implemented on the basis of technological processes [27-30], which allow creating only JFET GaAs field-effect transistors with a control p-n junction and bipolar GaAs p-n-p transistors.

The main objective of the proposed invention is to create a buffer amplifier implemented only on JFET gallium arsenide field-effect transistors with a control p-n junction and bipolar GaAs p-n-p transistors.

The task is achieved by the fact that in the buffer amplifier of Fig. 1 containing input 1 and output 2 of the device, the first 3 input field effect transistor with a control pn junction, the drain of which is matched with the first 4 power supply bus, the second 5 input field effect transistor with a control pn junction, the gate of which is connected to the gate of the first 3 input field effect transistor with a control pn junction and input 1 of the device, the drain is matched with the first bus 4 of the power supply, and the source is connected to the output 2 of the device, the reference current source 6, the first output of which is matched with the second bus 7 of the power source, new elements and connections are provided - a reference source current 6 is made on an additional field effect transistor 8 with a control pn junction, the gate of which is connected to the second 7 bus of the power source, and the source is connected to the second 7 bus of the power source through the first 9 additional resistor, the drain of the additional field effect transistor 8 with a control pn junction, which is the second output of the reference current source 6, connected to the source of the first 3 input field-effect transistor with a control pn transition through the potential matching circuit 10 and is connected to the base of the output pnp transistor 11, the emitter of which is connected to the output 2 of the device, and the collector is connected to the second 7 power supply bus.

The drawing of figure 1 shows a diagram of the buffer amplifier - the prototype.

In the drawing of FIG. 2 shows a diagram of the claimed device in accordance with paragraph 1 and paragraph 2 of the claims.

In the drawing of FIG. 3 shows a diagram of the claimed device in accordance with paragraph 3 of the claims.

In the drawing of FIG. 4 shows the static mode of the VU of FIG. 2 in LTspice environment at t = 27 °C, R ₁ = 20 kΩ, R ₂ = 15 kΩ, supply voltages ±10 V.

In the drawing of FIG. 5 shows graphs of the output voltage of the control unit of FIG. 4 from input V1 at t = 27°C, R1= 20 kΩ, R2 (5 kΩ, 50 kΩ, 100 kΩ, 10 MΩ), supply voltages ±10 V.

The gallium arsenide buffer amplifier of FIG. 2 contains input 1 and output 2 of the device, the first 3 input field effect transistor with a control pn junction, the drain of which is matched with the first 4 power supply bus, the second 5 input field effect transistor with a control pn junction, the gate of which is connected to the gate of the first 3 input field effect transistor with control pn transition and input 1 of the device, the drain is matched with the first 4 power supply bus, and the source is connected to the output 2 of the device, the reference current source 6, the first output of which is matched with the second 7 power supply bus. The reference current source 6 is made on an additional field-effect transistor 8 with a control p-n junction, the gate of which is connected to the second 7 power supply bus, and the source is connected to the second 7 power supply bus through the first 9 additional resistor. The drain of the additional field effect transistor 8 with a control pn junction, which is the second output of the reference current source 6, is connected to the source of the first 3 input field effect transistor with a control pn junction through a potential matching circuit 10 and is connected to the base of the output pnp transistor 11, the emitter of which is connected to output 2 device, and the collector is connected to the second 7 bus of the power source.

The two-terminal network R _n in the drawing of FIG. 2 onwards models the load properties of the VU.

In the drawing of FIG. 2, in accordance with paragraph 2 of the claims, the potential matching circuit 10 is made on the basis of a forward-biased p-n junction 12 on a bipolar p-n-p transistor, the collector of which is connected to the base.

In the drawing of FIG. 3, in accordance with paragraph 3 of the claims, the output pnp transistor 11 is made as a composite transistor on the elementary first 13 and second 14 auxiliary transistors connected according to the Darlington circuit, and the potential matching circuit 10 contains an auxiliary bipolar pnp transistor 15, as well as the second 16 and the third 17 additional resistors, and the second 16 additional resistor is connected between the emitter and the base of the auxiliary bipolar pnp transistor 15, and the third 17 additional resistor is connected between the base and the collector of the auxiliary bipolar pnp transistor 15.

Consider the operation of the proposed buffer amplifier of Fig. 2.

In static mode (R _n \u003d ∞, u in \ _u003d 0), the following currents and voltages are set in the circuit:

, (1)

, (one)

(2)

(2)

(3)

(3)

where I _s3 is the source current of the first 3 input field-effect transistor with a control pn junction;

- ток базы выходного p-n-p транзистора 11,

- base current of the output pnp transistor 11,

- ток эмиттера выходного p-n-p транзистора 11;

- emitter current of the output pnp transistor 11;

- коэффициент усиления по току базы выходного p-n-p транзистора 11;

- base current gain of the output pnp transistor 11;

U ₁₀ - static voltage on the bias circuit potentials 10;

U _z.3 - gate-source voltage of the first 3 input field-effect transistor with a control pn junction;

U _z.8 - gate-source voltage of the additional field-effect transistor 8 with a control pn junction;

U _eb.11 - emitter-base voltage of the output pnp transistor 11;

R ₉ - resistance of the first 9 additional resistor.

If in equation (3) we choose U ₁₀ =U _eb.12 =U _eb.11 , which is provided by the proposed circuitry of the BU, then the output voltage of the BU and its through current

U _out ≈ U _z.3 ≈ U _z.5 , (4)

I _well ≈ I ₀ . (five)

, то в нагрузке R_н образуется выходной ток

, максимальное значение которого I_н.max ⁽⁺⁾ определяется максимальным допустимым током истока второго 5 входного полевого транзистора с управляющим p-n переходом. При параллельном включении нескольких элементарных полевых транзисторов в качестве второго 5 входного полевого транзистора с управляющим p-n переходом численные значения максимального тока I_н.max ⁽⁺⁾ могут быть увеличены до заданных значений.If a positive input voltage is applied to the input of the control unit

, then in the load R _n an output current is formed

, the maximum value of which I _n.max ⁽⁺⁾ is determined by the maximum allowable source current of the second 5 input field-effect transistor with a control pn junction. When several elementary field-effect transistors are connected in parallel as the second 5th input field-effect transistor with a control pn junction, the numerical values of the maximum current I _н.max ⁽⁺⁾ can be increased to the specified values.

With a negative increment of the input voltage of the control unit, the current in the load R _n is provided through the emitter circuit of the output pnp transistor 11. As a result, the maximum negative current in the load R _n will be determined by the drain current of the additional field effect transistor 8 with a control pn junction

(6)

(6)

- статический ток стока дополнительного полевого транзистора 8 с управляющим p-n переходом.where

- static drain current of the additional field-effect transistor 8 with a control pn junction.

The use as an output p-n-p transistor 11 of the Darlington circuit on the elementary first 13 and second 14 auxiliary transistors (Fig. 3), allows you to increase the maximum current in the load at negative output voltages of the control unit:

(8)

(8)

- коэффициенты усиления по току базы первого 13 и второго 14 вспомогательных транзисторов.where

- current amplification factors of the base of the first 13 and second 14 auxiliary transistors.

However, for the temperature and radiation stability of the through current I _RMS in the circuit of Fig. 3, it is advisable to use a potential bias circuit 10 on an auxiliary bipolar pnp transistor 15, which provides

(9)

(nine)

For example, when R16=R17, from equation (9) one can find that

2 U _eb.15 ≈ U _eb.13 + U _eb.14 . (10)

Thus, with the same temperature and radiation voltage changes, the emitter-base of GaAs p-n-p transistors in the circuit of Fig. 3, the condition of stabilization of the through current of the control unit is fulfilled.

Computer simulation (Fig. 4, Fig. 5) shows that the proposed buffer amplifier, the circuitry of which is adapted for use in the range of low temperatures and exposure to penetrating radiation [26], has significant advantages in comparison with the known options for constructing a control unit when they are implemented within the framework of of the considered gallium arsenide technological process, which ensures the creation of only JFET field-effect transistors with a control pn junction and bipolar pnp transistors.

REFERENCES

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Claims (3)

1. Gallium arsenide buffer amplifier containing the input and output of the device, the first input field-effect transistor with a control pn junction, the drain of which is matched to the first power supply bus, the second input field-effect transistor with a control pn junction, the gate of which is connected to the gate of the first input field-effect transistor with a control pn junction and a device input, the drain is matched to the first power supply bus, and the source is connected to the device output, a reference current source, the first output of which is matched to the second power supply bus, characterized in that the reference current source is made on an additional field-effect transistor with control pn junction, the gate of which is connected to the second power supply bus, and the source is connected to the second power supply bus through the first additional resistor, the drain of the additional field-effect transistor with a control pn junction, which is the second output of the reference current source, is connected to the source of the first input field tra a resistor with a control p-n junction through a potential matching circuit and is connected to the base of the output p-n-p transistor, the emitter of which is connected to the output of the device, and the collector is connected to the second power supply bus. 2. Gallium arsenide buffer amplifier according to claim 1, characterized in that the potential matching circuit is made on the basis of a forward-biased p-n junction on a bipolar p-n-p transistor. 3. Gallium arsenide buffer amplifier according to claim 1, characterized in that the output pnp transistor is made as a composite transistor on elementary first and second auxiliary transistors connected according to the Darlington circuit, and the potential matching circuit contains an auxiliary bipolar pnp transistor, as well as the second and the third additional resistors, wherein the second additional resistor is connected between the emitter and base of the auxiliary bipolar pnp transistor, and the third additional resistor is connected between the base and collector of the auxiliary bipolar pnp transistor.

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