RU2767976C1 - Gallium arsenide power amplifier output stage - Google Patents

Abstract

FIELD: microelectronics.

SUBSTANCE: invention relates to the field of analog microelectronics and can be used as a gallium arsenide output stage of a power amplifier of various analog devices that can operate under conditions of penetrating radiation, low and high temperatures. The effect is achieved due to the fact that the gallium arsenide output stage of the power amplifier contains an input (1) and an output (2) of the device, an input (3) field-effect transistor with a control p-n junction, the gate of which is connected to the input (1) of the device, and the drain is connected to the first (4) power supply bus, the output (5) bipolar transistor, the emitter of which is connected to the output (2) of the device, and the collector is connected to the second (6) power supply bus. The gates of the first (7) and second (8) auxiliary field-effect transistors with a control p-n-junction are connected to the second (6) power supply bus. The drain of the first (7) auxiliary field-effect transistor with a control p-n-junction is connected to the base of the output (5) bipolar transistor. The gate of the second auxiliary field-effect transistor with a control p-n-junction is additionally connected to its source through the first (9) current-stabilizing two-pole. Additionally, the first (10) and second (11) additional bipolar transistors, as well as the first (12) and second (13) additional resistors are introduced into the gallium arsenide output stage of the power amplifier. The source of the input (3) field-effect transistor with a control p-n-junction is connected to the output (2) of the device, and its drain is connected to the first (4) power supply bus through the first (12) additional resistor and is connected to the emitter of the first (10) additional bipolar transistor. The emitter of the second (11) additional bipolar transistor is connected to the first (4) power supply bus through the second (13) additional resistor, and its base is connected to the base and collector of the first (10) additional bipolar transistor and is connected to the drain of the second (8) auxiliary field transistor with a control p-n-junction. The collector of the second (11) additional bipolar transistor is connected to the drain of the first (7) auxiliary field-effect transistor with a control p-n junction, the source of which is connected to the second (6) power supply bus through the third (14) additional resistor.

EFFECT: creating an output stage of a power amplifier implemented only on gallium arsenide JFET field-effect transistors with a control p-n junction and GaAs bipolar p-n-p transistors.

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Description

The invention relates to the field of analog microelectronics and can be used as a gallium arsenide output stage of a power amplifier of various analog devices that can operate under conditions of penetrating radiation, low and high temperatures.

A significant number of circuits for output stages of power amplifiers and buffer amplifiers (VC) are known, which are implemented on bipolar (BJT) and field-effect (JFet, CMOS, SOI, SOS, etc.) transistors, as well as when they are connected together [1-29]. In many applications, the VC scheme is adapted to specific technological processes and external influencing factors, for example, the influence of low temperatures or radiation, since. only in this case is the implementation of the limiting parameters of the VC provided.

Currently, in Russian and foreign microelectronics, increased attention is paid to gallium arsenide microcircuits [30–33]. This direction of creating an electronic component base is one of the most promising in the tasks of space instrumentation. However, the features of gallium arsenide technological processes [30–33] impose significant restrictions on the types of implemented transistors and their characteristics. So, for example, the gallium arsenide technological process mastered by US firms [30-33], as well as the Minsk Research Institute of Radio Materials (https://mniirm.by/), is focused on the manufacture of analog circuits containing only GaAs field-effect transistors with control pn junction and bipolar GaAs pnp transistors. The use of other semiconductor devices is not allowed. This imposes significant restrictions on the circuitry of analog devices oriented to a given technological process [30–33].

The closest prototype (Fig. 1) of the proposed device is the output stage of the power amplifier, presented in patent RU No. 2523947. It contains (Fig. 1) input 1 and output 2 of the device, input 3 field effect transistor with a control pn junction, the gate of which is connected to input 1 of the device, and the drain is connected to the first 4 bus of the power source, the output 5 is a bipolar transistor, the emitter of which is connected to the output 2 of the device, the collector is connected to the second 6 bus of the power source, and the gate of the first 7 auxiliary field-effect transistor with a control pn junction is connected to the second 6 power supply bus, and its drain is connected to the base of the output 5 bipolar transistor, the second 8 auxiliary field-effect transistor with a control pn-junction, the gate of which is connected to the second 6 power supply bus and connected to the source of the second 8 auxiliary field-effect transistor with a control pn- passing through the first 9 current-stabilizing two-terminal network.

A significant drawback of the prototype output stage is that it cannot be implemented on the basis of technological processes that allow creating only gallium arsenide JFET field-effect transistors with a control p-n junction and bipolar GaAs p-n-p transistors.

The main objective of the proposed invention is to create an output stage of a power amplifier implemented only on gallium arsenide JFET field-effect transistors with a control p-n junction and GaAs bipolar p-n-p transistors.

The task is achieved by the fact that in the output stage of the power amplifier of Fig. 1, containing input 1 and output 2 of the device, input 3 is a field effect transistor with a control pn junction, the gate of which is connected to input 1 of the device, and the drain is connected to the first 4 bus of the power source, output 5 is a bipolar transistor, the emitter of which is connected to output 2 of the device , the collector is connected to the second 6 power supply bus, and the gate of the first 7 auxiliary field-effect transistor with a control pn-junction is connected to the second 6 power supply bus, and its drain is connected to the base of the output 5 bipolar transistor, the second 8 auxiliary field-effect transistor with a control pn- junction, the gate of which is connected to the second 6 bus of the power source and connected to the source of the second 8 auxiliary field-effect transistor with a control pn-junction through the first 9 current-stabilizing two-terminal network, new elements and connections are provided - the first 10 and second 11 additional bipolar transistors are introduced into the circuit, and also the first 12 and second 13 additional resistors, and the source input 3 field effect transistor with a control pn junction is connected to output 2 of the device, the drain of the input 3 field effect transistor with a control pn junction is connected to the first 4 power supply bus through the first 12 additional resistor and connected to the emitter of the first 10 additional bipolar transistor, the emitter of the second 11 additional bipolar transistor is connected to the first 4 power supply bus through the second 13 additional resistor, the base of the second 11 additional bipolar transistor is connected to the base and collector of the first 10 additional bipolar transistor and is connected to the drain of the second 8 auxiliary field effect transistor with a control pn-junction, the collector of the second 11 additional bipolar transistor is connected to the drain of the first 7 auxiliary field effect transistor with a control pn junction, and the source of the first 7 auxiliary field effect transistor with a control pn junction is connected to the second 6 power supply bus through the third 14 additional resistor.

Figure 1 shows a diagram of the output stage of the power amplifier - the prototype.

In FIG. 2 shows a diagram of the proposed gallium arsenide output stage of the power amplifier.

In FIG. 3 shows a diagram of the inventive gallium arsenide output stage of the power amplifier for the case in accordance with claim 2 of the claims, when transistors 7 and 8 are made in a cascode structure.

In FIG. 4 shows a diagram of the proposed gallium arsenide output stage of the power amplifier in accordance with paragraph 3, paragraph 4 of the claims.

In FIG. 5 is a circuit diagram for simulating the gallium arsenide output stage of FIG. 2 in LTspice environment at t=27 ^o C, R1=350 Ohm, R2= 150 Ohm, R3=5.4 kOhm, R4= 11.5 kOhm, R5= 10 kOhm, V1=-1.2 V, Ep(±)= 10V.

In FIG. 6 shows the amplitude response of the output stage of FIG. 5 at t=27 ^o C, R1=350 Ohm, R2= 150 Ohm, R3=5.4 kOhm, R4= 11.5 kOhm, R5= 10 kOhm, V1=-1.2 V, Ep(±)= 10V.

In FIG. 7 shows in the LTspice environment a circuit for simulating the gallium arsenide output stage of Fig.4 ^for t=27 ° C, R1=350 Ohm, R2= 150 Ohm, R3=5.4 kOhm, R4= 11.5 kOhm, R5= 5 kOhm, V1= -1.17 V, Ep(±)= 10V.

In FIG. 8 shows the amplitude response of the output stage of FIG. 7 for t=27 ^o C, R1=350 Ohm, R2= 150 Ohm, R3=5.4 kOhm, R4= 11.5 kOhm, R5= 5 kOhm, V1=- V1=-1.17 V, Ep(±)= 10V, at Rn= 2 kOhm/ 20 kOhm/∞.

The gallium arsenide output stage of the power amplifier of FIG. 2 contains input 1 and output 2 of the device, input 3 is a field-effect transistor with a control pn junction, the gate of which is connected to input 1 of the device, and the drain is connected to the first 4 bus of the power source, output 5 is a bipolar transistor, the emitter of which is connected to output 2 of the device, the collector is connected to the second 6 bus of the power source, and the gate of the first 7 auxiliary field effect transistor with a control pn junction is connected to the second 6 bus of the power source, and its drain is connected to the base of the output 5 bipolar transistor, the second 8 auxiliary field effect transistor with a control pn junction , the gate of which is connected to the second 6 power supply bus and connected to the source of the second 8 auxiliary field-effect transistor with a control pn-junction through the first 9 current-stabilizing two-pole. The first 10 and second 11 additional bipolar transistors are introduced into the circuit, as well as the first 12 and second 13 additional resistors, and the source of the input 3 field effect transistor with a control pn junction is connected to the output 2 of the device, the drain of the input 3 field effect transistor with a control pn junction is connected with the first 4 power supply bus through the first 12 additional resistor and connected to the emitter of the first 10 additional bipolar transistor, the emitter of the second 11 additional bipolar transistor is connected to the first 4 power supply bus through the second 13 additional resistor, the base of the second 11 additional bipolar transistor is connected to the base and collector of the first 10 additional bipolar transistor and connected to the drain of the second 8 auxiliary field effect transistor with a control pn junction, the collector of the second 11 additional bipolar transistor is connected to the drain of the first 7 auxiliary field effect transistor with a control pn junction, etc. and than the source of the first 7 auxiliary field-effect transistor with a control p-n-junction is connected to the second 6 power supply bus through the third 14 additional resistor.

The two-terminal network R _n in the drawings of FIG. 2 and further models the properties of the VC load.

In FIG. 3, in accordance with paragraph 2 of the claims, the first 7 and second 8 auxiliary field-effect transistors with a control pn junction are made respectively in the form of cascode composite transistors with a control pn junction 15, 16 and 17, 18.

In FIG. 4, in accordance with paragraph 3 of the claims, the drain of the first 7 auxiliary field-effect transistor with a control p-n junction is connected to the base of the output 5 of the bipolar transistor through the source voltage follower 19.

In FIG. 4, in accordance with paragraph 4 of the claims, the source voltage follower 19 contains the first 20 and second 21 additional field effect transistors with a control pn junction, and the combined source of the first 20 additional field effect transistor with a control pn junction and the drain of the second 21 additional field effect transistor with the control pn junction is the output of the source voltage follower 19, the gate of the second 21 additional field effect transistor with a control pn junction is connected to the second 6 power supply bus, the source of the second 21 additional field effect transistor with a control pn junction is connected to the second 6 power supply bus through the auxiliary resistor 23, and the gate of the first 20 additional field-effect transistor with a control pn-junction is the input of the source voltage follower 19.

Consider the operation of the proposed output stage of Fig. 2.

In static mode (R _n =∞, u _in =0) in the circuit of Fig. 2 the following currents and voltages are set:

(1)

(one)

where U _eb.11 , U _eb.10 - emitter-base voltages of the second 11 and the first 10 additional bipolar transistors;

I ₇ \u003d U _zi.7 / R ₁₄ - static current of the first 7 auxiliary field effect transistor with a control pn junction;

U _z.7 - gate-source voltage of the first 7 auxiliary field-effect transistor with a control pn-junction;

– сквозной ток ВК при Rн=∞;

- through current VC at Rн=∞;

R ₁₂ , R ₁₃ , R ₁₄ - resistances of the first 12, second 13 and third 14 additional resistors;

– статический ток второго 8 вспомогательного полевого транзистора с управляющим p-n-переходом.

- static current of the second 8 auxiliary field-effect transistor with a control pn-junction.

From equation (1) it follows that when I ₇ =const, I ₈ =I _e.10 =const, U _eb.11 =U _eb.10 ≈const due to the choice of resistances of the first 12 and second 13 additional resistors in the circuit of FIG. 2 set the target values of the through current I _RMS .

, то в нагрузке R_н образуется выходной ток

, максимальное значение которого I_н.max ⁽⁺⁾ определяется максимальным допустимым током истока входного 3 полевого транзистора с управляющим p-n-переходом. В этом случае с помощью второго 11 дополнительного биполярного транзистора обеспечивается запирание по цепи базы выходного 5 биполярного транзистора, который может быть исключен из дальнейшего рассмотрения работы схемы в этом режиме. При параллельном включении нескольких элементарных полевых транзисторов в качестве входного 3 полевого транзистора с управляющим p-n-переходом численные значения максимального тока I_н.max ⁽⁺⁾ могут быть увеличены до заданных значений.If the input of the VC of Fig. 2 positive input voltage is applied

, then in the load R _n an output current is formed

, the maximum value of which I _n.max ⁽⁺⁾ is determined by the maximum allowable source current of the input 3 field effect transistor with a control pn-junction. In this case, with the help of the second 11 additional bipolar transistor, the base circuit of the output 5 bipolar transistor is locked, which can be excluded from further consideration of the operation of the circuit in this mode. With the parallel connection of several elementary field-effect transistors as an input 3 field-effect transistor with a control pn-junction, the numerical values of the maximum current I _n.max ⁽⁺⁾ can be increased to the specified values.

With a negative increment of the input voltage VK, the current in the load R _n is provided by the output 5 bipolar transistor. Due to the decrease in the drain current of the input 3 field-effect transistor with a control pn-junction, the static current of the second 11 additional bipolar transistor decreases, which leads to an increase in the base current of the output 5 bipolar transistor and, as a result, the output current in the load with a negative u _in ^(-) . As a result, the maximum negative current in the load R _n will be determined by the maximum drain current of the first 7 auxiliary field effect transistor with a control pn junction

(2)

(2)

At the same time, due to negative feedback, the source current of the input 3 field-effect transistor with a control pn-junction practically does not change (I U3 _≈const ) and, therefore, the increment in the output voltage in this VC mode corresponds to the increment in its input voltage u _in ^(-) . As a consequence, the maximum negative current in the load R _n will be determined by equation (2).

A feature of the proposed VC circuit is the presence of a common negative feedback relative to output 2 of the device, which ensures high linearity of the amplitude characteristic - the absence of a dead zone characteristic of VC class "AB".

In the diagram of Fig. 3, in accordance with paragraph 2 of the claims, the first 7 and second 8 auxiliary field-effect transistors with a control p-n junction are made according to the cascode structure on transistors 15, 16 and 17, 18, respectively. This increases the loop gain along the VC negative feedback circuit, and also reduces the effect of voltage instabilities on the first 4 and second 6 power supply buses on the operation of the circuit.

In the diagram of Fig. 4, in accordance with paragraphs 3 and 4 of the claims, a source voltage follower 19 was introduced, which helps to increase the loop gain in the negative feedback circuit of the VK, and also allows you to obtain higher values of the maximum current in the load I _n.max ^{(- )} .

To reduce the numerical values of the resistance of the first 12 additional resistor, the first 10 additional bipolar transistor in the circuits of FIG. 3 and FIG. 4 can be made in the form of a parallel connection of several elementary bipolar transistors. In this case, the numerical values of the resistance of the first 12 additional resistor may be close to zero.

Computer simulation (Fig. 5 - Fig. 8) shows that the proposed output stage, the circuitry of which is adapted for use in the range of low temperatures and exposure to penetrating radiation [29], has significant advantages in comparison with the known options for constructing a VC when they are implemented within the framework of of the considered gallium arsenide technological process, which provides the creation of JFET field effect transistors with a control pn junction and bipolar pnp transistors.

REFERENCES

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27. Horowitz P., Hill W. The art of circuitry: Per. from English - Ed. 2nd. - M .: Publishing house BINOM. 2014. - 704 p. Rice. 3.26, fig. 3.28, fig. 3.29.

28. Patt Boonyaporn, Varakorn Kasemsuwan. A High Performance Class AB CMOS Rail to Rail Voltage Follower // ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on, pp. 161-163.

29. Element base of radiation-resistant information-measuring systems: monograph / N.N. Prokopenko, O.V. Dvornikov, S.G. Krutchinsky; under total ed. d.t.s. prof. N.N. Prokopenko; FGBOU VPO "South-Ros. state University of Economics and Service”. - Mines: FGBOU VPO "YURGUES", 2011. - 208 p.

30. M. Fresina, "Trends in GaAs HBTs for wireless and RF," 2011 IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Atlanta, GA, USA, 2011, pp. 150-153. doi: 10.1109/BCTM.2011.6082769.

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33 Peatman W. et al. InGaP-Plus™: advanced GaAs BiFET technology and applications // CS MANTECH Conference, May 14-17, 2007, Austin, Texas, USA. pp. 243-246.

Claims (4)

1. Gallium arsenide output stage of the power amplifier, containing the input (1) and output (2) of the device, the input (3) field-effect transistor with a control pn junction, the gate of which is connected to the input (1) of the device, and the drain is connected to the first ( 4) power supply bus, the output (5) bipolar transistor, the emitter of which is connected to the output (2) of the device, the collector is connected to the second (6) power supply bus, and the gate of the first (7) auxiliary field-effect transistor with a control pn-junction is connected to the second (6) power supply bus, and its drain is connected to the base of the output (5) bipolar transistor, the second (8) auxiliary field-effect transistor with a control pn-junction, the gate of which is connected to the second (6) power supply bus and connected to the source of the second (8) auxiliary field-effect transistor with a control pn-junction through the first (9) current-stabilizing two-pole, characterized in that the first (10) and second (11) additional bipolar transistors are introduced into the circuit, as well as the first (12) and second (13) additional resistors, and the source of the input (3) field-effect transistor with a control pn-junction is connected to the output (2) of the device , the drain of the input (3) field-effect transistor with a control pn-junction is connected to the first (4) power supply bus through the first (12) additional resistor and is connected to the emitter of the first (10) additional bipolar transistor, the emitter of the second (11) additional bipolar transistor is connected with the first (4) power supply bus through the second (13) additional resistor, the base of the second (11) additional bipolar transistor is connected to the base and collector of the first (10) additional bipolar transistor and is connected to the drain of the second (8) auxiliary field effect transistor with control pn -transition, the collector of the second (11) additional bipolar transistor is connected to the drain of the first (7) auxiliary field-effect transistor ora with a control p-n-junction, and the source of the first (7) auxiliary field-effect transistor with a control p-n-junction is connected to the second (6) power supply bus through the third (14) additional resistor. 2. The gallium arsenide output stage of the power amplifier according to claim 1, characterized in that the first (7) and second (8) auxiliary field-effect transistors with a control pn junction are made respectively in the form of cascode composite transistors with a control pn junction (15) , (16) and (17), (18). 3. The gallium arsenide output stage of the power amplifier according to claim 1, characterized in that the drain of the first (7) auxiliary field-effect transistor with a control p-n junction is connected to the base of the output (5) bipolar transistor through the source voltage follower (19). 4. The gallium arsenide output stage of the power amplifier according to claim 3, characterized in that the source voltage follower (19) contains the first (20) and second (21) additional field-effect transistors with a control pn junction, and the combined source of the first (20) additional field effect transistor with a control pn junction and the drain of the second (21) additional field effect transistor with a control pn junction are the output of the source voltage follower (19), the gate of the second (21) additional field effect transistor with a control pn junction is connected to the second (6) power supply bus, the source of the second (21) additional field effect transistor with a control pn junction is connected to the second (6) power supply bus through an auxiliary resistor (23), and the gate of the first (20) additional field effect transistor with a control pn junction is the input of the source voltage follower (19).

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