RU2725781C1 - Fault-tolerant self-synchronous single-cycle rs-trigger with a single spacer - Google Patents

Abstract

FIELD: data processing.SUBSTANCE: invention is intended for construction of fault-tolerant self-synchronizing trigger, register and computing devices, digital information processing systems. In a trigger circuit comprising eight n-type CMOS transistors, eight p-type CMOS transistors, two paraphrase data inputs with a single spacer and two biphase information outputs, two OR-AND-NOR elements are introduced, hysteresis trigger and indicator output, paraphrase inputs and biphase outputs of RS trigger are connected to inputs of OR-AND-NOT elements, outputs of which are connected to inputs of hysteresis trigger, whose output is connected to indicator output of RS-trigger.EFFECT: technical result consists in providing self-synchronized operation of trigger by implementation of indicatability of all its elements.1 cl, 1 dwg

Description

Fail-safe self-synchronous single-cycle RS-trigger with a single spacer refers to pulse and computer technology and can be used to build fault-tolerant self-synchronous trigger, register and computing devices, digital information processing systems.

Known self-synchronous single-cycle RS-trigger with a single spacer [1, Fig. 3], containing an AND-AND element and two OR-AND-NOT elements.

A disadvantage of the known device is its low resistance to failure, which allows the trigger to switch to the opposite state when exposed to ionizing radiation, heavy charged particles, protons and neutrons.

Closest to the proposed solution in technical essence and adopted as a prototype is a DICE-type RS-trigger [2, Fig. 3 (a)] containing eight n-type CMOS transistors and eight p-type CMOS transistors.

The disadvantage of the prototype is the inability to use it in self-synchronous operation due to the lack of indication of the end of switching elements of the RS-trigger circuit.

The problem solved in the invention is to ensure self-synchronous operation of the trigger by implementing the display of all its elements.

This is achieved by the fact that in a single-ended RS-flip-flop containing eight n-type CMOS transistors, eight p-type CMOS transistors, two paraphase information inputs with a single spacer and two biphasic information outputs, the sources and substrates of all p-type transistors are connected to the power bus, the drains of the first and second p-type transistors are connected to the drain of the first n-type transistor, the gates of the sixth p-type and n-type transistors and the direct component of the first biphase output, the drains of the third and fourth p-type transistors are connected to the drain of the second transistor n -type, with the gates of the seventh p-type transistor and the fifth n-type transistor and a direct component of the second biphasic output, the drains of the fifth and sixth p-type transistors are connected to the drain of the fifth n-type transistor, the gates of the third p-type transistor and the first n- transistor type and inverse component of the first biphasic output, the drains of the seventh and eighth p-type transistors are connected to the drain of the sixth n-type transistor, the gates and the second p- and n-type transistors and the inverse component of the second biphase output, the source of the first n-type transistor is connected to the drain of the third n-type transistor, the source of the second n-type transistor is n-connected to the drain of the fourth n-type transistor, the source of the fifth the n-type transistor is connected to the drain of the seventh n-type transistor, the source of the sixth n-type transistor is connected to the drain of the eighth n-type transistor, the sources of the third, fourth, seventh and eighth n-type transistors and the substrate of all n-type transistors are connected to the bus the ground, the gates of the first p-type transistor and the fourth n-type transistor are connected to the direct component of the first paraphase information input with a single spacer, the gates of the fourth p-type transistor and the third n-type transistor are connected to the direct component of the second paraphase information input with a single spacer, the gates of the fifth p-type transistor and the eighth n-type transistor are connected to the inverse component of the first paraphase information of the input with a single spacer, the gates of the eighth p-type transistor and the seventh n-type transistor are connected to the inverse component of the second paraphase information input with a single spacer, two OR-AND-NOT elements, a hysteresis trigger (G-trigger) and RS indicator output are introduced -trigger, with two inputs of the first group of inputs OR of the first element OR-AND-NOT connected to the direct component of the second paraphase information input with a single spacer and the inverse component of the second biphasic output of the RS-trigger, two inputs of the second group of inputs OR of the first element OR-AND- NOT connected to the direct component of the second biphasic output of the RS-flip-flop and the inverse component of the second paraphase information input with a single spacer, the two inputs of the first group of inputs OR of the second element OR-AND-NOT connected to the direct component of the first paraphase information input with a single spacer and the inverse component of the first RS-biphasic output, two inputs of the second group of inputs OR second of the OR-AND-NOT element are connected to the direct component of the first biphasic output of the RS-trigger and the inverse component of the first paraphase information input with a single spacer, the outputs of the first and second OR-AND-NOT elements are connected to the inputs of the G-trigger, the output of which is connected to the indicator RS trigger output.

The proposed device has significant features that distinguish it from the prototype and ensure the achievement of the claimed technical result. Indeed, the use of the OR-AND-NOT element to form an indicator output is also known in other self-synchronous triggers. But only the use of two elements OR-AND-NOT connected to the information inputs and outputs of a self-synchronous single-cycle RS-trigger and the inputs of the G-trigger in this way, allowed to achieve the effect expressed by the purpose of the invention.

The indicated essential features are distinctive, since the indicated structural connections are not known in similar technical solutions.

The concept of "paraphase" used in the text of this application is defined as follows. A signal is considered to be paraphase, represented by two components - a pair of variables {X, XB}, which in the active phase have mutually inverse values: {X = 0, XB = 1} or {X = 1, XB = 0}. The transition of a paraphase signal from one static operating state to the opposite operating state can be carried out in two ways.

The first method involves the use of a paraphase signal with a spacer: when the transition to the next operating state is necessarily preceded by the transition to the third static state - the spacer (inactive or blanking state). If the state {1,1} is used as the spacer, then they say that a paraphase signal with a single spacer is used, and if the state is {0,0}, then a paraphase signal with a zero spacer is used. The spacer state is a static state, switching to which in self-synchronous circuitry should be fixed by the indicator of the end of the transition process, in this case, the end of switching to the spacer state.

The second method involves the use of a paraphase signal without a spacer. In this case, the transition from one working static state to another is carried out through a dynamic (short-term) state: {1,1} or {0,0}, - called a transit state.

The term "biphasic" used in the text of this application is defined as follows. A signal is considered biphasic, which is the output of {Q, QB} bistable cell (BJ) - RS-trigger on two logical elements with cross-connections. In the static phase, its components have mutually inverse values: {Q = 0, QB = 1} or {Q = l, QB = 0}. The transition of a biphasic signal from one static operating state to the opposite operating state is carried out through an intermediate dynamic (transit) state. Transit state: {zero - Q = QB = 0} or {single - Q = QB = 1}, is determined by the type of logic elements in the base unit.

The materials of this application are about the use of a paraphase signal with a single spacer as an information input, in the future - just a paraphase signal, and a biphasic signal with a single transit state.

In FIG. Figure 1 shows a diagram of a fail-safe self-synchronous single-cycle RS-trigger with a single spacer. The circuit contains eight p-type MOSFETs 1–8, eight n-type MOSFETs 9–16, a power bus 17, a ground bus 18, line 19 and inverse 20 components of the first information paraphase input with a single spacer, line 21 and inverse 22 components of the second information paraphase input with a single spacer, direct 23 and inverse 24 components of the first biphasic output, direct 25 and inverse 26 components of the second biphasic output, indicator output 27, elements OR-AND-NOT 28-29 and G-trigger 30, sources and the substrates of all p-type transistors 1-8 are connected to the power bus 17, the drains of the first 1 and second 2 p-type transistors are connected to the drain of the first p-type transistor 9, the gates of the sixth p-type 6 and n-type transistors 14 and direct component 23 of the first biphasic output, the drains of the third 3 and fourth 4 p-type transistors are connected to the drain of the second n-type transistor 10, the gates of the seventh p-type transistor 7 and the fifth n-type transistor 13, and the direct component of the second biphase of the output, the drains of the fifth 5th and sixth 6th p-type transistors are connected to the drain of the fifth 13th n-type transistor, the gates of the third 3th p-type transistor and the first 9th n-type transistor and the inverse component 24 of the first biphase output, the drains of the seventh 7th and 8th 8 p-type transistors are connected to the drain of the sixth 14 n-type transistor, gates of the second p-type transistors 2 and n-type 10 and the inverse component 26 of the second biphase output, the source of the first n-type transistor 9 is connected to the drain of the third n-type transistor 11 , the source of the second n-type transistor 10 is connected to the drain of the fourth n-type transistor 12, the source of the fifth n-type transistor 13 is connected to the drain of the seventh n-type transistor 15, the source of the sixth n-type transistor 14 is connected to the drain of the eighth n-type transistor 16, the sources of the third 11, fourth 12, seventh 15 and eighth 16 n-type transistors and the substrate of all n-type transistors are connected to the ground bus, the gates of the first p-type transistor 1 and the fourth n-type transistor 12 are connected are connected to the direct component 19 of the first paraphase information input with a single spacer, the gates of the fourth p-type transistor 4 and the third n-type transistor 11 are connected to the direct component 21 of the second paraphase information input with a single spacer, the gates of the fifth p-type transistor 5 and the eighth transistor n-type 16 are connected to the inverse component 20 of the first paraphase information input with a single spacer, the gates of the eighth p-type transistor 8 and the seventh n-type transistor 15 are connected to the inverse component 22 of the second paraphase information input with a single spacer, the RS-trigger indicator output is introduced 27, two elements OR-AND-NOT 28-29 and Г-flip-flop 30, moreover, two inputs of the first group of inputs OR of the first element OR-AND-NOT 28 are connected to the direct component 21 of the second paraphase information input with a single spacer and an inverse component 26 of the second biphasic RS-trigger output, two inputs of the second group of inputs OR of the first element OR-AND-NOT 28 p connected to the direct component 25 of the second biphasic output of the RS flip-flop and the inverse component 22 of the second paraphase information input with a single spacer, the two inputs of the first group of inputs OR of the second element OR-AND-NOT 29 are connected to the direct component 19 of the first paraphase information input with a single spacer and the inverse component 24 of the first biphasic output of the RS flip-flop, the two inputs of the second group of inputs OR of the second element OR-AND-NOT 29 are connected to the direct component 23 of the first biphasic output of the RS flip-flop and the inverse component 20 of the first paraphase information input with a single spacer, the outputs of the first 28 and the second 29 elements OR-AND-NOT connected to the inputs of the G-trigger 30, the output of which is connected to the indicator output 17 of the RS-trigger.

The scheme works as follows. The first and second paraphase inputs are logically identical. The first and second biphase outputs are also logically identical. The use of identical pairs of inputs and outputs ensures fault tolerance of the information transmitted and stored in the trigger. Both biphasic trigger outputs will switch to a new identical state only when both paraphase inputs go into the same operating phase. The inputs have a single spacer. This means that the spacer value "1" of any component of any input is not able to change the state of the biphase outputs of the trigger.

Denote line 19 and inverse 20 the components of the first paraphase input as S1 and R1, the components 21 and 22 of the second paraphase input as S2 and R2; direct 23 and 24 inverse components of the first biphasic output as Q1 and QB1, components 25 and 26 of the second biphasic output as Q2 and QB2; indicator output 27 as I. Let the trigger be in the spacer in the initial state: R1 = R2 = S1 = S2 = 1, - and store the state: Q1 = Q2 = 1, QB1 = QB2 = 0. Open transistors 2, 3, 11-16; closed transistors 1, 4-10. The outputs of the elements 28 and 29 low logic level. The indicator output confirms the end of trigger switching into the spacer: I = 0. Let the signal R1 = 0 arrive at the trigger input, and the rest of the inputs remain unchanged. A low level at the gates of transistors 5 and 16 will lead to the unlocking of transistor 5 and locking of transistor 16. An open transistor 5 will “pull” output QB1 to the power supply (logical unit level), but open transistors 13 and 15 will prevent this. The sizes of the p-type and n-type transistors in this circuit are selected so that the open p-type transistor is not able to "pull" the series-connected open n-type transistors. Then the output level of QB1 will still correspond to a logical zero and the state of the RS-trigger will not change. Only after the input R2 is switched to a value identical to the input Rl (R2 = 0), which unlocks the p-type 8 transistor and locks the n-type 15 transistor, can the transistor 5 raise the output potential of QB1 to the level of a logical unit. At the same time, the output QB2 switches to the state of the logical unit due to the open transistor 8 and the closed transistor 16. This will cause subsequent switching in the circuit: locking transistors 2 and 3, unlocking the transistors 9 and 10, then switching the outputs Q1 and Q2 to the state of logical zero (Q1 = Q2 = 0). As a result, the trigger will go into a new state Q1 = Q2 = 0, QB1 = QB2 = 1. In accordance with the new values of the inputs and outputs of the trigger, the outputs of the elements 28 and 29 will switch to the value of the logical unit and initiate the switch of the G-trigger also to the state of the logical unit (I = 1), which will confirm the successful completion of the switching of the self-synchronous single-cycle trigger to a new operating state.

The fault tolerance of a trigger is confirmed by its response to a single cause that causes a logical failure - switching one component of one biphasic trigger output to the opposite state. Suppose, for example, a trigger is in the same initial state: R1 = R2 = S1 = S2 = 1, Q1 = Q2 = 1, QB1 = QB2 = ^: 0, I = 0, and a heavy charged particle flying through the drain region of the transistor n-type 13, caused an ionization current that charged the parasitic capacitance of the output QB1 to the level of a logical unit. This will lead to the locking of the transistor 3 and the unlocking of the transistor 10. Since the transistor 9 is closed, the state of the output Q1 will not change, since it is maintained by the open transistor 2, and the state of the output Q2 will remain the same (Q2 = l) due to stray charge storage this output when the transistor 10 is closed. The ionization current ends quite quickly, since the transistors 13 and 15 remain open and cause the resorption of excess carriers in the semiconductor body. Output QB1 returns to its original state (QB1 = 0) and the trigger continues to successfully store its state. Short-term switching of the output QB1 to the state of a logical unit does not cause the switching of elements 28, 29 and 30, and the indicator output 27 of the trigger retains its value, notifying the receivers that the trigger is still in the spacer and its state cannot be used.

The features of this scheme compared with the prototype are as follows.

The elements OR-AND-NOT and G-trigger, combining the paraphase inputs and biphasic outputs and forming the indicator output of a single-cycle RS-trigger, provide control of the trigger operation phases, indicating the correspondence of the state of the phase inputs to the state of the biphase outputs in the working phase and indicating the switching of inputs to the spacer. This ensures self-synchronization of switching a single-cycle RS-trigger from the working phase to the spacer and vice versa.

Thus, the proposed device implements the self-synchronous operation of a single-cycle RS-trigger by ensuring the display of all its conclusions and elements. The objective of the invention is achieved.

Sources

[1] Stepchenkov Yu.A., Dyachenko Yu.G., Rozhdestvensky Yu.G., Petrukhin B.C. One-cycle self-synchronous RS-trigger with a preset. Patent No. 2390092. Publ. in B.I., 2010, No. 14. - 18 p.

[2] Katunin Yu.V., Stenin V.Ya., Stepanov P.V. Modeling the characteristics of the CMOS trigger elements of two-phase logic, taking into account the separation of charge when exposed to individual nuclear particles // Microelectronics, 2014, V.43, No. 2. - S. 104-117.

Claims (1)

Fail-safe self-synchronous single-cycle RS-trigger with a single spacer, containing eight CMOS n-type transistors, eight CMOS p-type transistors, two paraphase information inputs with a single spacer and two biphasic information outputs, the sources and substrates of all p-type transistors connected to the bus power supply, the drains of the first and second p-type transistors are connected to the drain of the first n-type transistor, the gates of the sixth p-type and n-type transistors and the direct component of the first biphasic output, the drains of the third and fourth p-type transistors are connected to the drain of the second n- transistor type, the gates of the seventh p-type transistor and the fifth n-type transistor and a direct component of the second biphase output, the drains of the fifth and sixth p-type transistors are connected to the drain of the fifth n-type transistor, the gates of the third p-type transistor and the first n-type transistor and the inverse component of the first biphasic output, the drains of the seventh and eighth p-type transistors are connected to the drain of the sixth tra n-type transistor, the gates of the second p-type and n-type transistors and the inverse component of the second biphase output, the source of the first n-type transistor is connected to the drain of the third n-type transistor, the source of the second n-type transistor is connected to the drain of the fourth n-type transistor , the source of the fifth n-type transistor is connected to the drain of the seventh n-type transistor, the source of the sixth n-type transistor is connected to the drain of the eighth n-type transistor, the sources of the third, fourth, seventh and eighth n-type transistors and the substrate of all n-type transistors connected to the ground bus, the gates of the first p-type transistor and the fourth n-type transistor are connected to the direct component of the first paraphase information input with a single spacer, the gates of the fourth p-type transistor and the third n-type transistor are connected to the direct component of the second paraphase information input with a single spacer, the gates of the fifth p-type transistor and the eighth n-type transistor are connected to the inverse component of the first pa phase information input with a single spacer, the gates of the eighth p-type transistor and the seventh n-type transistor are connected to the inverse component of the second paraphase information input with a single spacer, characterized in that two OR-AND-NOT elements, a hysteresis trigger and an indicator are introduced into the circuit an output, the two inputs of the first group of inputs OR of the first element OR-AND-NOT connected to the direct component of the second paraphase information input with a single spacer and the inverse component of the second biphasic output of the RS flip-flop, two inputs of the second group of inputs OR of the first element OR-AND-NOT connected to the direct component of the second biphasic output of the RS-flip-flop and the inverse component of the second paraphase information input with a single spacer, the two inputs of the first group of inputs OR of the second element OR-AND-NOT connected to the direct component of the first paraphase information input with a single spacer and the inverse component of the first biphasic RS trigger output, two inputs the second group of inputs OR the second element OR-AND-NOT connected to the direct component of the first biphasic output of the RS-trigger and the inverse component of the first paraphase information input with a single spacer, the outputs of the first and second elements OR-AND-NOT connected to the inputs of the hysteresis trigger, the output of which connected to the indicator output of the RS-trigger.

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