RU2629639C1 - Digital driver with end-to-end tranfsfers - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: digital storage with end-to-end transfers contains a clock generator 1, a first memory register 2, an adder 3, a second memory register 4, an accelerated transfer scheme 5. The input of the first memory register 2 is the digital input of the digital storage, and its output is the output of the second memory register.

EFFECT: possibility of forming packets of rectangular pulses with a specified period of repetition of a stack of rectangular pulses, which consists of overflow pulses due to through transfer in the adder.

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Description

The invention relates to electronic computer technology, is intended for the synthesis of packets of rectangular pulses and can be used in radar and navigation systems.

The closest technical solution (prototype) is a digital drive containing the first, second and third memory registers, adder [1].

A positive technical result - the ability to form packs of rectangular pulses with a given repetition period of a packet of rectangular pulses, which consists of overflow pulses due to pass-through transfer in the adder - is achieved by the fact that a digital drive with pass-through transfers contains a first memory register connected in series; the first adder input, the second memory register, the input of the digital storage device is the input of the first memory register, and its output is the output of the second memory register, and the new one is that a clock generator and an accelerated transfer circuit are introduced; moreover, the output of the second memory register is directly connected to the second input of the adder; the outputs of the accelerated transfer circuit are connected to the inputs of generation and propagation of the transfer G and P sections of the adder; the output of the clock generator is connected to the clock inputs of the first and second memory registers.

A digital drive with end-to-end transfers contains a clock generator 1, a first memory register 2, an adder 3, a second memory register 4, and an accelerated transfer circuit 5 (Fig. 1). The input of the first memory register 2 is the digital input of a digital storage device, and its output is the output of the second memory register.

For example, a 16-bit digital drive with end-to-end transfers contains the first memory register 2, consisting of two 8-bit sections, the output of which is connected to the first input of the adder 3, consisting of four 4-bit sections, the output of which is connected to the input of the second memory register 3 consisting of two 8-bit sections, the output of the latter goes to the second input of the adder 3, and is also the output of a digital drive; accelerated transfer circuit 5 is connected to the inputs P and G of each section of the adder 3; the clock generator 1 is connected to the clock inputs of the first and second memory registers 2 and 4.

Digital storage works as follows.

The clock generator 1 generates a sequence of rectangular pulses of the form "meander", used to synchronize the operation of the memory registers of the digital drive.

The code A _{i is} received at the input of the first memory register 2, which will determine the repetition rate of a packet of rectangular pulses at the output of the second memory register 4. Code A _{i is} received at the first input of adder 3, from which the result of the sum goes to the input of the second memory register 4, output which is connected to the second input of the adder 3.

The accelerated transfer scheme serves to increase the speed of the sections of the adder 3 and allows you to fight the race of fronts with a large capacity of the digital drive.

With the arrival of the first clock pulse code A _i is accumulated in adder 3 plus the transfer unit three times to be stored in the second memory register. The signal at the output of the least significant bit of the second memory register 4 is shown in FIG. 2.

Thus, a packet of rectangular pulses is formed at the output of the digital storage device. This signal at the outputs of the second memory register 4 can be used in radar and navigation systems.

Literature

1. RF patent №2058659, IPC Н03 В 19/00. Digital frequency synthesizer / Ryabov I.V., Fishchenko P.A. Claim 09/23/1993. Publ. 04/20/1996. Bull. No. 11. - 4 p. (prototype).

Claims (1)

A digital drive with end-to-end transfers, containing the first memory register connected in series, the first adder input, the second memory register; the input of the digital memory is the input of the first memory register, and its output is the output of the second memory register, characterized in that a clock pulse generator and an accelerated transfer circuit are introduced, the output of the second memory register directly connected to the second input of the adder, the outputs of the accelerated transfer circuit connected to the inputs generation and distribution of the transfer of G and P sections of the adder, the output of the clock generator is connected to the clock inputs of the first and second memory registers.

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