RU2536385C1 - Digital synthesiser for generating multi-frequency telegraphy signals - Google Patents

Abstract

FIELD: physics, computer engineering.

SUBSTANCE: invention relates to electronic-computer engineering and radio engineering and is intended for synthesis of multi-frequency telegraphy signals and can be used in modern adaptive communication systems. The digital synthesiser for generating multi-frequency telegraphy signals comprises a first memory register 1, a second memory register 2, an adder 3, a digital storage 4, a code converter 5, a digital-to-analogue converter (DAC) 6, a low-pass filter 7, a reference generator 8 and a formation and delay unit 9.

EFFECT: generation of multi-frequency telegraphy signals and faster operation.

1 dwg

Description

The invention relates to electronic computer technology and radio engineering, is intended for the synthesis of multi-frequency telegraphy signals and can be used in modern adaptive communication systems.

Known digital frequency synthesizers containing a clock generator, a delay unit, the first and second memory registers, a counter with a preset, the first and second read-only memory blocks, DAC, low-pass filter, the first and second digital drives [1].

The closest technical solution (prototype) is a digital frequency synthesizer containing a reference generator and a delay unit; shift register, digital storage, code-sine functional converter, digital-to-analog converter (DAC), low-pass filter (LPF) [2].

A positive technical result - the possibility of generating multi-frequency telegraphy signals and increasing speed - is achieved due to the fact that in a digital synthesizer for generating multi-frequency telegraphy signals containing a reference oscillator and a generation and delay unit connected in series; first memory register; a digital drive, a code converter, a digital-to-analog converter and a low-pass filter connected in series, the output of which is the analog output of a digital synthesizer, and its first digital input is the input of the first memory register; the outputs of the formation and delay unit are connected to the clock inputs of the digital storage and digital-to-analog converter, respectively, new is that a second memory register and an adder are introduced; the output of the second memory register is connected to the second input of the adder; the output of the first memory register is connected to the first input of the adder, and the output of the adder is connected to the input of a digital storage device; the input of the second memory register is the second digital input of a digital synthesizer.

A digital synthesizer for generating multi-frequency telegraphy signals contains a first memory register 1, a second memory register 2, an adder 3, a digital drive 4, a code converter 5, a digital-to-analog converter (DAC) 6, a low-pass filter (LPF) 7, the output of which is the analog output of a digital a synthesizer; a reference generator 8 and a block of formation and delay 9; the first and second digital inputs of the digital synthesizer are the information inputs of the first and second memory registers 1 and 2, respectively.

Digital synthesizer works as follows.

The information input of the first register of memory 1 receives the code A _i , simultaneously the input of the second register of memory 2 receives the code B _j . These codes are added in adder 3 and code C

will determine the initial frequency of the synthesized signal.

The reference generator 8 generates a sinusoidal signal of the reference frequency, from which clock pulses of the meander shape are generated in the generation and delay unit 9, which are spaced in time and serve to synchronize the operation of the digital drive 4 and the digital-to-analog converter 6.

With the arrival of the first clock pulse, code C is loaded into digital storage 4, the summation of which will change according to the formula

The sum code S is supplied to the code converter 5, which from the S code generates a sin (S) code, which is fed to the information inputs of the DAC 6, where a step-by-step sinusoidal signal is generated, determined by the code C. The low-pass filter 7 passes only the first harmonic of the generated signal to the output .

If we assume that ω ₀ = C = A _i + B _j is the initial frequency of the synthesized signal, Δt = T is the duration of the clock interval, then the output of the low-pass filter 7 will generate a signal described by the formula:

where U _m is the signal amplitude.

The frequency of the synthesized signal ω ₀ will be determined by the codes A _i and B _j received at the inputs of the first and second memory registers 1 and 2, which are digital inputs of a digital synthesizer.

Therefore, by changing the codes A _i and B _j , it is possible to control the frequency of the digital synthesizer and generate multi-frequency telegraphy signals. The speed of tuning the frequency of the generated signal will not exceed one clock interval, so the speed of this digital synthesizer is higher compared to the prototype.

Literature

1. RF patent No. 2058659. IPC Н03В 19/00. Digital frequency synthesizer / Ryabov I.V., Fishchenko P.A. Claim 09/23/1993. Publ. 04/20/1996. Bull. No. 11. - 4 p.

2. Patent No. 2452085 of the Russian Federation, IPC H03L 7/00. Digital Computing Synthesizer for Multi-Frequency Telegraphy / Ryabov I.V., Dedov A.N., Yuriev P.M., Ryabova S.A., Tolmachev S.V. Claim 07/07/2011. Publ. 05/27/2012. Bull. No. 15. 4 sec (prototype).

Claims (1)

A digital synthesizer for generating multi-frequency telegraphy signals, comprising a reference oscillator and a generation and delay unit connected in series; first memory register; a digital drive, a code converter, a digital-to-analog converter and a low-pass filter connected in series, the output of which is the analog output of a digital synthesizer, and its first digital input is the input of the first memory register; the outputs of the formation and delay unit are connected to the clock inputs of a digital storage device and a digital-to-analog converter, respectively, characterized in that a second memory register and an adder are introduced; the output of the second memory register is connected to the second input of the adder; the output of the first memory register is connected to the first input of the adder, and the output of the adder is connected to the input of a digital storage device; the input of the second memory register is the second digital input of a digital synthesizer.