RU2294054C1 - Digital quadrature-output computing synthesizer - Google Patents

Abstract

FIELD: computer and radio engineering; radar, navigation, and adaptive communication systems.

SUBSTANCE: proposed device has standard generator, delay unit, two memory registers, two digital storage devices, variable-ratio divider, two code converters, two digital-to-analog converters, two low-pass filters, and inverter.

EFFECT: ability of synthesizing frequency-modulated quadrature signals.

1 cl, 3 dwg

Description

The invention relates to electronic computer technology and radio engineering, is intended for the synthesis of coherent quadrature frequency-modulated signals and can be used in radar, navigation systems and adaptive communication systems.

Known digital frequency synthesizers containing a clock pulse generator, a delay unit, two read-only memory blocks, a preset counter, two memory registers, two digital storage devices, a code converter, a digital-to-analog converter, a low-pass filter and a pulse shaper [1].

The closest technical solution (prototype) to the proposed one is a digital frequency synthesizer, containing a series-connected clock generator and a delay unit, series-connected the first permanent memory unit and a counter with preset, connected in series the second permanent memory unit, the second memory register, the second digital storage device , first memory register, first digital storage, code converter, digital-to-analog converter, lower hour filter from whose output is the output of the digital frequency synthesizer, and inputs are the address inputs of the first and second memory blocks DC [2].

However, in known digital frequency synthesizers there is no possibility of obtaining coherent quadrature signals.

The invention allows to expand the functionality of a digital synthesizer and makes it possible to synthesize coherent quadrature frequency-modulated signals.

The positive effect - providing the possibility of synthesis of coherent quadrature frequency-modulated signals - is achieved due to the fact that the digital computer synthesizer contains a reference generator and a delay unit connected in series; two memory registers; two digital drives; variable divider divider; connected in series to a second digital storage device, a first code converter, a first digital-to-analog converter and a first low-pass filter, the output of which is the analog output of the entire device; the outputs of the delay unit are connected to the clock inputs of a divider with a variable division ratio, a second digital storage device and a first digital-to-analog converter; the output of the divider with a variable division coefficient is connected to the input of the serial transfer of the first digital drive, and the new one is that an inverter is introduced into the digital computer synthesizer; connected in series to a second code converter, a second digital-to-analog converter, a second low-pass filter, the output of which is the second analog output of a digital computer synthesizer, and its inputs are the inputs of the first and second memory registers; the output of the first memory register is connected to the input of the first digital drive, the output of the latter is connected to the input of the second digital drive, the highest output bit of which is connected to the inversion control input of the first code converter and the inverter input, the output of which is connected to the inversion control input of the second code converter; the output of the second memory register is connected to the input of the divider with a variable division ratio; the output of the second digital drive is connected to the input of the second code converter; the output of the delay unit is connected to the clock input of the second digital-to-analog converter.

Figure 1 shows the structural diagram of a digital computer synthesizer, figure 2 - graphs of the output signals of the DAC.

The digital computational synthesizer (Fig. 1) contains a reference (reference) generator 1, a delay unit 2, a first memory register 3, a first digital storage 4, a second digital storage 5, a first code converter 6, a first digital-to-analog converter 7, a first low-pass filter 8 , the second memory register 9, a divider with a variable division factor 10, an inverter 11, a second code converter 12, a second digital-to-analog converter 13, a second low-pass filter 14.

Digital computing synthesizer works as follows.

At the input of the first register of memory 3, the initial frequency code C _{i is} received, and at the input of the second register of memory 9, a code D _k determining the division coefficient of the divider 10 and the rate of change of the frequency of the digital computer synthesizer.

The reference generator 1 generates a reference signal of a sinusoidal shape, which is fed to the input of the delay unit 2, forming a time-spaced sequence of rectangular pulses of the form "meander", which are fed to the input of the divider with a variable division factor 10, the inputs of the first and second digital drives 4 and 5 , the inputs of the first and second digital-to-analog converters 7 and 13, and serve to synchronize the operation of a digital computer synthesizer.

With the first clock pulse at time t ₁ (FIG. 2), the initial frequency code C _i from the first memory register 3 is recorded in the first digital storage device 4, and the code of the division coefficient D _k from the second memory register 9 is recorded in the divider with a variable division coefficient 10.

Then, with each clock pulse, code A at the output of the first digital drive 4 will change as follows:

This code A goes to the input of the second digital drive 5, the summation of which will change according to the formula:

The high-order bit of the sum code S _SGN is significant and goes to the inversion control input of the first code converter 6 and to the inverter 11 input. From the inverter output, the signal _{SG SGN} goes to the input of the second code converter 12, the remaining N high-order bits (where N is the DAC bit depth) the first and second converters of codes 6 and 12 are fed to the information inputs of the first and second DACs 7 and 13, respectively.

If S _SGN = 0, then the first binary DAC 7 receives the direct binary code of the sum, and the second DAC 13 receives the inverse binary code of the sum. If S _SGN = 1, then the inverse code of the sum is received on the first DAC 7, and the direct code of the sum on the second DAC 13.

At the outputs of the DACs 7 and 13, step signals of a "triangular" shape are formed, phase shifted by 180 °. Low pass filters 8 and 14 have cutoff frequencies f _cp <f _m / 2, where f _m is the clock frequency. Thus, low-pass filters 8 and 14 pass only the first harmonic of the synthesized signals.

If we assume that ω ₀ = C _i is the initial cyclic frequency;

0.5 ω` = 1 / D _k is the rate of change of the cyclic frequency;

Δt = T is the duration of the clock interval, then at the outputs of the low-pass filters 8 and 14 there will be LFM signals whose amplitude varies according to the formula:

where U _m is the signal amplitude.

Thus, two coherent quadrature LFM signals are generated in a digital computer synthesizer.

Literature

1. Patent No. 2149503 of the Russian Federation, MKI N 03 V 19/00, Digital frequency synthesizer / Ryabov I.V., Ryabov V.I. - Declared. 04/13/1999. Publ. 05/20/2000. Bull. No. 14.

2. Patent No. 2058659 of the Russian Federation, MKI N 03 V 19/00, Digital frequency synthesizer / Ryabov IV, Fischenko P.A. - Declared. 09/23/1993. Publ. 04/20/1996 Bull. No. 11 (prototype).

Claims (1)

Digital computing synthesizer with quadrature outputs, containing a series-connected reference generator and a delay unit; two memory registers; digital drive; variable divider divider; connected in series to a second digital storage device, a first code converter, a first digital-to-analog converter and a first low-pass filter, the output of which is the analog output of the entire device; the outputs of the delay unit are connected to the clock inputs of a divider with a variable division ratio, a second digital storage device and a first digital-to-analog converter; the output of the divider with a variable division coefficient is connected to the input of the serial transfer of the first digital drive, characterized in that an inverter is introduced into the digital computer synthesizer; connected in series to a second code converter, a second digital-to-analog converter, a second low-pass filter, the output of which is the second analog output of a digital computer synthesizer, and its inputs are the inputs of the first and second memory registers; the output of the first memory register is connected to the input of the first digital drive, the output of the latter is connected to the input of the second digital drive, the highest output bit of which is connected to the inversion control input of the first code converter and the inverter input, the output of which is connected to the inversion control input of the second code converter; the output of the second memory register is connected to the input of the divider with a variable division ratio; the output of the second digital drive is connected to the input of the second code converter; the output of the delay unit is connected to the clock input of the second digital-to-analog converter.

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