RU2726833C1 - Digital computer synthesizer with suppression of crosstalk - Google Patents

Abstract

FIELD: electronic engineering; radio engineering.SUBSTANCE: invention is intended for synthesis of frequency-modulated and phase-shift keyed signals and can be used in radar, navigation and communication systems. Digital computing synthesizer comprises (Fig. 1) reference generator 1, a forming and delay unit 2, memory register 3, a digital frequency storage 4, frequency correction unit 5, first adder 6, digital phase accumulator 7, phase correction unit 8, second adder 9, a code-sinus function converter 10, a digital-to-analogue converter (DAC) 11. Digital input of digital computer synthesizer is input of memory register, and its analog output – output of DAC.EFFECT: technical result is possibility of crosstalk suppression and incidental amplitude modulation.1 cl, 1 dwg

Description

The invention relates to electronic computers and radio engineering, is intended for the synthesis of complex frequency-modulated signals and can be used in radar, navigation and communication systems.

Known digital frequency synthesizers containing a clock pulse generator, a delay unit, two permanent memory units, a preset counter, two memory registers, two digital storage devices, a code converter, a DAC, a low-pass filter and a pulse shaper [1,2].

The closest technical solution (prototype) to the proposed one is a digital synthesizer of frequency-modulated signals, containing a clock pulse generator and a delay unit, a constant memory unit, two memory registers, two digital storage devices, a code converter, a DAC, a low-pass filter, two adders, a phase error corrector , frequency error corrector, divider with variable division ratio [3].

However, prior art digital computational synthesizers do not provide crosstalk rejection.

EFFECT: possibility of forming complex frequency-modulated signals with suppression of parasitic amplitude modulation.

The technical result is achieved due to the fact that in a digital computational synthesizer with suppression of crosstalk, containing a serially connected reference generator and a block of formation and delay; serially connected first memory register, digital frequency storage, first input of the first adder, digital phase storage, first input of the second adder; a digital-to-analog converter (DAC), the DAC output being the analog output of a digital computational synthesizer; the outputs of the formation and delay unit are connected to the clock inputs of the digital frequency storage, digital phase storage and digital-to-analog converter; the digital input of the digital computational synthesizer is the input of the memory register, and new is the fact that a functional converter and frequency and phase correction blocks are introduced; while the output of the second adder is connected to the input of the functional converter, the output of the latter is connected to the input of the DAC; the output of the functional converter is connected to the input of the frequency correction unit, the output of which is connected to the second input of the first adder; the output of the first adder is connected to the input of the phase correction unit, the output of the latter is connected to the second input of the second adder, the output of which is connected to the input of the functional converter.

The digital computational synthesizer contains a reference generator 1, a shaping and delay unit 2, a memory register 3, a digital frequency storage 4, a frequency correction unit 5, a first adder 6, a digital phase 7 accumulator, a phase correction unit 8, a second adder 9, a functional code converter. sine 10, digital-to-analog converter (DAC) 11.

The digital input of the digital computational synthesizer is the input of the memory register, and its analog output is the output of the DAC.

A digital computational synthesizer contains a serially connected reference generator 1 and a shaping and delay unit 2; serially connected memory register 3, digital frequency storage 4, the first input of the first adder 6, digital storage of phase 7, the first input of the second adder 9, functional converter 10, DAC 11, the output of which is the analog output of the DSC, and its digital input is the input of the memory register 3.

The output of the first adder 6 is also connected to the input of the phase correction unit 8, the output of the latter is connected to the second input of the second adder 9.

The output of the functional converter 10 is also connected to the input of the frequency correction unit 5, the output of the latter is connected to the second input of the first adder 6; the outputs of the formation and delay unit 2 are connected to the clock inputs of the frequency and phase storage units and the DAC.

The digital computational synthesizer works as follows. The reference generator 1 generates a sinusoidal signal of the reference frequency, from which, in the formation and delay unit 2, a series of clock pulses of the "meander" shape are formed, which serve to synchronize the main units of the DSC: digital frequency storage 4, digital storage phase 7 and DAC 11.

Let at the moment t _{0 the} code of the initial frequency C _i arrives at the input of the memory register 3. At time t _{1, the} code C _{i is} written into the digital frequency storage (DFS) 4.

At time t _{2, the} code C _i from the DSC 4 is fed to the input of the first adder and then fed to the input of the digital phase accumulator (DSC) 7. At the same time, the code C _{i is} fed to the input of the phase correction unit 3, and then through the adder 9 to the functional converter 10.

Thus, starting from time t _1, the sum code will change as follows:

S1 = C _i × T (1)

The amount code in CNF 7 will change according to the formula:

S2 = C _i × T + T ² (2)

Starting from the moment of time t _{3, the} code of the sum S2 enters the input of the frequency correction unit 5. Then the code of the sum S3 at the output of the first adder 6 will change according to the formula:

S3 = (C _i + K _f ) T + T ₂ (3)

Starting from the moment of time t _{4, the} code of the sum S4 at the output of the second adder 9 will change according to the formula:

S4 = (C _i + K _f ) T + (I + K _φ ) T ² (4)

Further, the sum code S4 is fed to the input of the functional converter code-sine 10 and the sin (S4) code is fed to the digital-to-analog converter 11, where an FM signal of a "stepped" form is generated:

u _c (t) = U ₀ sin [(C _i + K _f ) T + (I + K _φ ) T ² )], (5)

where U ₀ is the amplitude of the DSS output signal.

If you enter the following designations:

f ₀ = C _i + K _f is the initial frequency code, f ′ = 1 + K _φ is the rate of frequency change, ∆t = T is the clock interval. then the FM signal can be described by the expression: u _c (t) = U ₀ sin (f ₀ t + f ′ t ² ). (6)

Thus, a chirp signal is formed in the DSC, which lacks the PAM, which is usually the case with the well-known DSC and DSC structures.

The advantages of the proposed digital computational synthesizer can also be attributed to: high frequency tuning rate, fast phase change when forming complex FM signals.

Literature

1. Ryabov I.V., Yuriev P.M. Recursive frequency synthesizer for generating signals with linear frequency modulation // Fundamental research. 2012. No. 9-3. S. 685-689.

2. RF patent No. 2149503. IPC H03L 7/18. Digital synthesizer of frequencies / Ryabov I.V., Ryabov V.I., Golub D.V. Appl. 04.13.1999. Publ. 05/20/2000. Bul. No. 4. - 6 p.

3. RF patent No. 2166833. IPC H03L 7/18. Digital synthesizer of frequency-modulated signals / Ryabov I.V., Ryabov V.I., Golub D.V. Appl..09.02.2000. Publ. 05/10/2001. Bul. No. 6. - 6 p. (prototype).

Claims (1)

Digital computational synthesizer with crosstalk suppression, containing a series-connected reference generator and a shaping and delay unit, series-connected first memory register, digital frequency storage, first input of the first adder, digital phase accumulator, first input of the second adder, digital-to-analog converter (DAC), and the DAC output is an analog output of a digital computational synthesizer, the outputs of the formation and delay unit are connected to the clock inputs of a digital frequency storage, a digital phase storage and a digital-to-analog converter, a digital input of a digital computational synthesizer is a memory register input, characterized in that a functional converter and frequency correction blocks are introduced and phase, while the output of the second adder is connected to the input of the functional converter, the output of the latter is connected to the input of the DAC, the output of the functional converter is connected to the input of the frequency correction unit, out From which is connected to the second input of the first adder, the output of the first adder is connected to the input of the phase correction unit, the output of the latter is connected to the second input of the second adder, the output of which is connected to the input of the functional converter.

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