RU2491710C1 - Frequency agile digital computational synthesiser - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: digital computational synthesiser has a reference generator 1 and a formation and delay unit 2, a first memory register 3, a first counter 4, a code multiplier 5, a digital storage 6, a code converter 7, a digital-to-analogue converter (DAC) 8, a low-pass filter 9, the output of which is the analogue output of the digital computational synthesiser; a second memory register 10, a second counter 11, a third memory register 12, a variable-ratio divider 13; inputs of the first, second and third memory registers are the digital inputs of the digital computational synthesiser.

EFFECT: high rate of adjusting operational frequency.

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Description

The invention relates to electronic computer technology and radio engineering, is intended for the synthesis of frequency-modulated signals and can be used in radar, navigation and modern adaptive communication systems.

Known digital frequency synthesizers containing two blocks of permanent storage of a digital drive, code multiplier, preset counter, code converter, memory register, digital-to-analog converter, low-pass filter, clock generator, delay unit [1].

The closest technical solution (prototype) is a digital frequency synthesizer containing a clock pulse generator, a delay unit, a constant memory unit, a preset counter, a code multiplier, a digital storage device, a digital-to-analog converter, a low-pass filter, a memory register [2].

However, the known digital frequency synthesizers do not have a high frequency tuning rate and have limited functionality when generating signals with linear frequency modulation.

The technical result - increasing the speed of the frequency tuning - is achieved by the fact that in a digital computer synthesizer containing a series-connected reference generator and a block of formation and delay; a second memory register, the input of which is the digital input of a digital computational synthesizer; a first counter, a code multiplier, a digital storage device, a code converter, a digital-to-analog converter and a low-pass filter connected in series, the output of which is the analog output of a digital computer synthesizer; the outputs of the formation and delay unit are connected to the clock inputs of the multiplier, multiplier, and product of the code multiplier, as well as to the clock inputs of the digital storage device and digital-to-analog converter, the new one being that the first and third memory register, the second counter, and the divider with a variable division coefficient are introduced, the digital inputs of the digital computational synthesizer are the inputs of the first and third memory registers; the output of the first memory register is connected to the input of the first counter; the output of the second memory register is connected to the input of the second counter, and the output of the second counter is connected to the input of the code multiplier factor; the output of the third memory register is connected to the input of the divider with a variable division coefficient, the output of the latter is connected to the clock input of the second counter; the outputs of the formation and delay unit are connected to the corresponding clock inputs of the first counter, a divider with a variable division coefficient.

The digital computational synthesizer contains a reference generator 1 and a block for generating and delaying 2, a first memory register 3, a first counter 4, a code multiplier 5, a digital drive 6, a code converter 7, a digital-to-analog converter (DAC) 8, a low-pass filter (LPF) 9, the output of which is the analog output of a digital computer synthesizer, a second memory register 10, a second counter 11, a third memory register 12, a divider with a variable division ratio 13; the inputs of the first, second and third memory registers are the digital inputs of a digital computer synthesizer.

A digital computing synthesizer comprises a series-connected reference generator 1 and a block of formation and delay 2; connected in series are the first memory register 3, the first counter 4, the code multiplier 5, the digital memory 6, the code converter 7, the digital-to-analog converter 8 and the low-pass filter 9, the output of which is the analog output of a digital computer synthesizer; sequentially connected the second memory register 10 and the second counter 11, the output of which is connected to the input of the multiplier of the code multiplier 5; the third memory register 12 and the divider with a variable division ratio 13 are connected in series, the output of the latter is connected to the clock input of the first counter 11; the outputs of the formation and delay unit 2 are connected to the corresponding clock inputs of the multiplier, multiplier, and product of the code multiplier 5, digital storage 6, digital-to-analog converter 8, first counter 4, divider with a variable division coefficient 13; the digital inputs of the digital computational synthesizer are the inputs of the first, second and third memory registers 3, 10 and 12.

A digital computational synthesizer works as follows: The reference oscillator 1 generates a sinusoidal clock signal, from which a meander waveform is generated in the generation and delay unit 2, spaced in time and used to synchronize the operation of the digital computational synthesizer.

At the inputs of the first memory register 3, the code X _i (multiplied code) is received, the code Y _j (the code of the multiplier) is received at the input of the second memory register 10, and the code D _{k is} received at the input of the third memory register 12.

These codes are written accordingly: code X _i - in the first counter 4, code Y _j - in the second counter 11, code D _k - in the divider with a variable division coefficient 13.

With the first clock pulse at time t _1, codes X _i and Y _j enter the inputs of the multiplier and multiplier of the code multiplier 5.

Starting from the second clock pulse - moment t ₂ and then the product code (frequency code) in the code multiplier will change according to the formula:

$$R=(X_i+T)\times Y_j=X_i\times Y_j+Y_j\times T(\mathrm{one})$$

The amount code in digital storage 6 (phase code) will change according to the formula:

$$S=P\times T=X_i\times Y_j\times T+Y_j+T^2(2)$$

If we introduce the notation

ω ₀ = X _i × Y _j is the initial cyclic frequency;

ω '= 0.5Y _j is the rate of change of frequency;

T = Δt is the clock interval,

then the phase of the synthesized signal of the DAC will be described by the formula:

$${\varphi }_i=S={\omega }_{0}t+0.5\omega \text{'}\text{'}{t}^2(3)$$

The phase code φ _{i is} supplied to the code converter 7, with the most significant digit SGN being the sign bit fed to the inversion control input of the code converter 7, and the remaining bits through the code converter 7 are fed to the information inputs of the DAC 8.

If SGN = 0, then the direct phase code arrives at DAC 8, and if SGN = 1, then the reverse phase code arrives at DAC 8.

In DAC 8, a “stepped” signal of a “triangular” shape is formed. After filtering in the low-pass filter 9, which has a cut-off frequency equal to half the clock frequency, a signal with linear frequency modulation is formed at the output of the DAC:

$$u_c(t)=U_{0}sin\left({\omega }_{0}t+0.5\omega \text{'}\text{'}{t}^2\right)(\mathrm{four}\text{)}$$

The divider with a variable division factor 13 is used to control the rate of change of frequency, the larger the code D _k , the lower the rate of change of frequency.

In the proposed digital computational synthesizer, it is possible to further control the frequency of the output signal, for example, transmit an information message in the LFM mode by changing the multiplier code Y _j .

This IHD allows you to generate a signal with a quadratic law of frequency change. If you start both counters, then in the first counter the code will change according to the formula: X = X _i + T,

and in the second counter according to the formula: Y = Y _j + T / D _k

Then the signal frequency will change according to the formula:

$$P=(X_i+T)\times \left(Y_j+T/D_k\right)=X_i\times Y_j+X_i\times T/D_k+Y_j\times T+T^2/D_k(5)$$

In this case, the phase of the synthesized signal will change according to the formula:

$$S=(X_i+T)\times \left(Y_j+T/D_k\right)\times T=X_i\times Y_j\times T+X_i\times T^2/D_k+Y_j\times T^2+T^3/D_k(6\text{)}$$

Thus, this digital computational synthesizer has wider functionality and allows you to generate signals with a linear and quadratic law of frequency change, and it is also possible to transmit an information message in the LFM mode.

Literature

1. A.S. USSR No. 1774464. MKI H03B 19/00. Digital frequency synthesizer / Ryabov I.V., Ryabova N.V., Uryadov V.P. Decl. 08/30/1990. Publ. 11/07/1992. Bull. No. 41. - 4 p.

2. RF patent No. 2143173. IPC H03L 7/18, H03B 19/00. Digital frequency synthesizer / Ryabov I.V., Ryabov V.I. Claim 02/04/1999. Publ. 12/20/1999. Bull. Number 35. - 6 p. (prototype).

Claims (1)

A digital computational synthesizer comprising a series-connected reference generator and a block for generating and delaying; a second memory register, the input of which is the digital input of a digital computational synthesizer; a first counter, a code multiplier, a digital storage device, a code converter, a digital-to-analog converter and a low-pass filter connected in series, the output of which is the analog output of a digital computer synthesizer; the outputs of the formation and delay unit are connected to the clock inputs of the multiplier, multiplier and product of the code multiplier, as well as to the clock inputs of the digital storage device and digital-to-analog converter, characterized in that the first and third memory register, the second counter, and the divider with a variable division coefficient are introduced, the digital inputs of the digital computational synthesizer are the inputs of the first and third memory registers; the output of the first memory register is connected to the input of the first counter; the output of the second memory register is connected to the input of the second counter, and the output of the second counter is connected to the input of the code multiplier factor; the output of the third memory register is connected to the input of the divider with a variable division coefficient, the output of the latter is connected to the clock input of the second counter; the outputs of the formation and delay unit are connected to the corresponding clock inputs of the first counter, a divider with a variable division coefficient.