RU2204196C2 - Digital synthesizer of phase-modulated signal - Google Patents

Abstract

FIELD: electronic engineering. SUBSTANCE: digital synthesizer has read-only memory unit, two digital storage devices, three memory registers, variable-ratio divider, frequency standard, delay unit, code converter, digital-to- analog converter, low-frequency filter, gate multivibrator, and two adders. EFFECT: provision for on-line setting of desired phase-modulation mechanism for synthesized signal. 2 dwg

Description

 The invention relates to electronic computer technology, is intended for the synthesis of signals with phase and frequency modulation and can be used in adaptive communication systems, in radar and communication systems with software tuning of the operating frequency.

 Known digital frequency synthesizers containing a clock pulse generator, a delay unit, a permanent memory unit, a preset counter, a code multiplier, a digital storage device, a code converter, a digital-to-analog converter, a low-pass filter, a memory register [1].

 The closest technical solution (prototype) to the proposed one is a digital frequency synthesizer containing a series-connected clock generator and a delay unit, series-connected the first permanent memory unit and a counter with preset, connected in series the second permanent memory unit, the second memory register, the second digital storage device , first memory register, first digital storage, code converter, digital-to-analog converter, lower hour filter from whose output is the output of the digital frequency synthesizer, and inputs are the address inputs of the first and second memory blocks DC [2].

 However, in known frequency synthesizers there is no way to quickly change the phase of the synthesized signal.

 The invention allows to expand the functionality of a digital synthesizer, makes it possible to quickly install the necessary law of phase modulation of the synthesized signal.

 A positive effect - the ability to quickly set the necessary law of phase modulation of the output signal compared to existing synthesizers - is achieved due to the fact that the digital synthesizer of phase-modulated signals contains a permanent storage unit, the address inputs of which are inputs of the synthesizer, the first and second digital drives, the first and second the second memory registers, a divider with a variable division coefficient, a series-connected reference generator and a delay unit, the outputs of which are connected to the clock inputs of the first and second memory registers, a divider with a variable division coefficient, the output of which is connected to the serial transfer input of the first digital storage device, a code converter, a digital-to-analog converter, a low-pass filter, the output of which is an analog output of a digital phase-modulated signal synthesizer, moreover new is that a standby multivibrator, first and second adders, a third memory register are introduced, with digital synthesizer inputs The phase-modulated signal detector is also the information inputs of the first, second and third memory registers and the input of the standby multivibrator, the output of which is connected to the installation inputs of the first and second digital drives and a divider with a variable division ratio, a read-only memory unit, a first digital drive, a first adder are connected in series, a second digital storage device, a second adder, a code converter; the output of the first memory register is connected to the information input of the divider with a variable division coefficient, the output of the second memory register is connected to the second input of the first adder, the output of the third memory register is connected to the second input of the second adder, the highest output bit of the sum of the latter is connected to the inversion control input of the code converter, and the clock inputs of the third memory register, the first and second digital drives and digital-to-analog converter are connected to the corresponding outputs of the delay unit.

 The digital phase-modulated signal synthesizer (Fig. 1) contains a reference (reference) generator 1, a delay unit 2, a standby multivibrator 3, a read-only memory 4, a first digital storage 5, a first adder 6, a second digital storage 7, a second adder 8, a code converter 9, a digital-to-analog converter 10, a low-pass filter 11, a first memory register 12, a divider with a variable division coefficient 13, a second memory register 14, a third memory register 15.

 A digital synthesizer of phase-modulated signals consists of series-connected read-only memory 4, a first digital storage 5, a first adder 6, a second digital storage 7, a second adder 8, a code converter 9, a digital-to-analog converter 10, a low-pass filter 11, the output of which is the analog output of the synthesizer ; a series-connected reference generator 1 and a delay unit 2, the outputs of which are connected respectively to the clock inputs of the first, second and third memory registers 12, 14, 15, a divider with a variable division factor 13, first and second digital drives 5 and 7, a digital-to-analog converter 10; the synthesizer inputs are the address inputs of the read-only memory 4, the information inputs of the first, second and third memory registers 12, 14 and 15, the input of the standby multivibrator 3, while the output of the standby multivibrator 3 is connected to the installation inputs of the first and second digital drives 5 and 7 and the divider with a variable division ratio 13, the output of which is connected to the serial transfer input of the first digital drive 5, and the information inputs are to the outputs of the first memory register 12, the outputs of the second memory register 14 are connected to the second inputs of the first adder 6, the outputs of the third memory register 15 are connected to second inputs of the second adder 8, the output rank Senior amount latter is connected to the control input of the inverse code converter 9.

 A digital synthesizer of phase-modulated signals operates as follows.

 The reference generator 1 generates a clock signal of a sinusoidal shape, which is fed to the input of the delay unit 2, forming a spaced apart sequence of rectangular pulses of the form "meander" (figa), received at the clock inputs of the first, second, third memory registers 12, 14, 15, a divider with a variable division ratio 13, the first and second digital drives 5 and 7, a digital-to-analog converter 10 and used to synchronize the synthesizer and reduce switching noise at its output.

Let at the moment t ₁ (Fig.2b) a start pulse arrives at the input of the waiting multivibrator 3, forming a pulse of a negative polarity setting (Fig. 2c), which arrives at the installation inputs of the first and second digital drives 5 and 7, a divider with a variable division ratio 13.

At time t ₂ (Fig. 2a, c), codes are recorded: C _i - in the first digital drive 5, depending on the address code at the input of the read-only memory 4, D _k - first memory register 12, And _j - in the second memory register 14, B ₁ - into the third memory register 15.

At the end of the installation pulse (Fig.2c), the sum code (C _i + A _j ) from the outputs of the first adder 6 is supplied to the inputs of the second digital storage device 7, and the code D _{k is} recorded in a divider with a variable division factor 13 (Fig.2d).

At time t ₃ , the sum code is recorded from the outputs of the second digital storage device 7 to the first inputs of the second adder 8, the second inputs of which receive the code B ₁ from the third memory register 15 (Fig.2e).

Starting from the following clock pulses, the result at the outputs of the first digital drive 5 will change according to the formula:
Sl = C _i + T / D _k , (1)
where T = 0,1,2,3,4, ... is the number of the clock pulse.

At the outputs of the first adder 6, the sum code will change as follows:
S2 = C _i + T / D _k + A _j , (2).

Then at the outputs of the second digital drive 7, the accumulation result will change according to the formula:
S3 = (C _i + T / D _k + A _j • T = (C _i + A _j ) • T + T ² / D _k , (3).

At the outputs of the second adder 8, the sum code will change as follows:
S4 = (C _i + A _j ) • T + T ² / D _k + B _i , (4).

 The high order bit SGN of the sum code S4 is fed to the inverse control input of code converter 9, and the remaining bits of the sum code are connected to the information inputs of code converter 9. If SGN = 0, then the direct binary sum code S4 is sent to digital-to-analog converter 10, and if SGN = 1 , then is the inverse code of the sum S4.

 From the output of the digital-to-analog converter 10, the analog signal is fed to a low-pass filter 11, which passes only the first harmonic of the synthesized signal to the output.

If you accept that
ω _n = 2πf _n = C _i + A _j is the initial cyclic frequency of the synthesized signal,
0,5ω ′ = πf ′ = 1 / D _k is the rate of change of the cyclic frequency of the signal,
φ ₀ = B ₁ - the initial phase of the signal, then the output of the low-pass filter 11 will be a signal whose amplitude will vary by the formula:
u (t) = U _m sin (ω _n t + 0,5ω′t ² + φ ₀ ), (5)
where U _m is the signal amplitude.

If A _j = 0, B ₁ = 0, then a signal with linear frequency modulation will be generated at the output of the synthesizer. By changing the codes A _j , B ₁ at the inputs of the second and third memory registers 14 and 15, it is possible to modulate the synthesized signal in frequency and phase, respectively.

Literature
1. Patent 2143173 of the Russian Federation. MKI N 03 B 19/00. Digital frequency synthesizer / Ryabov I.V., Ryabov V.I. - Declared. 02/04/1999. Publ. 12/20/1999. BI 35.

 2. Patent 2058659 of the Russian Federation. MKI N 03 B 19/00. Digital frequency synthesizer / Ryabov I.V., Fischenko P.A. - Declared. 09/23/1993. Publish 04/20/1996. Bull. 11. (Prototype).

Claims (1)

 A digital phase-modulated signal synthesizer containing a constant storage unit, the address inputs of which are the inputs of the synthesizer, the first and second digital storage devices, the first and second memory registers, a divider with a variable division coefficient, a reference oscillator and a delay unit connected in series to the clock inputs of the first and the second memory registers, a divider with a variable division ratio, the output of which is connected to the input of the serial transfer of the first digital storage Firing, series-connected code converter, digital-to-analog converter, low-pass filter, the output of which is the analog output of a digital phase-modulated signal synthesizer, characterized in that the standby multivibrator, the first and second adders, the third memory register are introduced, while the inputs of the digital phase-modulated signal synthesizer are also information inputs of the first, second and third memory registers and the input of the standby multivibrator, the output of which is connected to the inputs of the installation of the second and second digital storage devices and a divider with a variable division ratio, a read-only memory unit, a first digital storage device, a first adder, a second digital storage device, a second adder and a code converter are connected in series, the output of the first memory register is connected to the information input of a divider with a variable division ratio, output the second memory register is connected to the second input of the first adder, the output of the third memory register is connected to the second input of the second adder, the highest output bit is sum we are connected to the inverter control input of the code converter, and the clock inputs of the third memory register, the first and second digital drives and the digital-to-analog converter are connected to the corresponding outputs of the delay unit.

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