RU2535931C1 - Radar receiver with control device - Google Patents

Abstract

FIELD: radio, communication.

SUBSTANCE: in radar receiver comprising n (n is an integer number) of receiving channels and the reference frequency generator, the control device is integrated. Each receiving channel comprises an intermediate frequency amplifier, an analogue-digital converter, a digital quadrature generator, a permanent storage device, a digital heterodyning device, an adapter, a digital adder, and a data transmitter. The control device comprises two transceivers SMI, two generators of signals, seven buffers, two signal drivers, and a level converter.

EFFECT: generation of control signals synchronizing the work of units included in the on-board radar.

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Description

The invention relates to the receiving path of radar or similar systems and is intended to provide high-performance primary digital signal processing in real time in all operating modes of the airborne radar station.

One of the main tasks in radar systems and in information transmission devices is to ensure synchronization of the operation of all components of radar systems at various operating modes specified by the onboard computer system.

The closest device selected as a prototype for the claimed technical solution is a radar receiver with high resolution channels [RF patent 2344436, IPC: G01S 7/285, 2009], containing n (n is an integer) of the receiving channels, each of which includes an intermediate frequency amplifier, analog-to-digital converter, digital quadrature driver, read-only memory, digital heterodyning device, adapter, digital adder and data transmitter. In addition, the radar receiver includes a driver of the reference frequencies and n receiving channels of high resolution. The disadvantage of this radar receiver is that it lacks the means to ensure synchronization of the components of the radar.

The technical result to which the claimed invention is directed is the creation of a radar receiver with a control device that generates control signals that synchronize the operation of the units included in the radar.

The technical result is achieved by the fact that a control device is introduced into the radar receiver containing n (n is an integer) of the receiving channels and the driver of the reference frequencies. Each receiving channel includes an intermediate-frequency amplifier, analog-to-digital converter, digital quadrature driver, read-only memory, digital heterodyning device, adapter, digital adder and data transmitter. The control device comprises: a first transceiver, a first signal conditioner, a second transceiver, a second signal conditioner, a first, second, third, fourth, fifth, sixth and seventh buffers, first and second signal drivers, a level converter. The first input of the intermediate frequency amplifier is the input of the receiving channel. The output of the intermediate frequency amplifier is connected to the first input of the analog-to-digital converter, the first output of which is connected to the first input of the digital quadrature driver. The output of the digital quadrature driver is connected to the first input of the digital heterodyning device, the output of which is connected to the first input of the digital adder. The output of the digital adder is connected to the first input of the data transmitter, the output of which is the output of the receive channel. The second output of the analog-to-digital converter is connected to the second inputs of the digital quadrature driver, digital heterodyning device, digital adder and data transmitter. The output of the read-only memory is connected to the third input of the digital heterodyning device. The first output of the adapter is connected to the fourth input of the digital heterodyning device, and the second output is connected to the third input of the digital adder. The inputs and outputs of the intermediate frequency amplifier and adapter are connected to the interface of the central processor. The input of the reference frequency driver is the input of the reference signal. The first output of the reference frequency driver is connected to the second input of the analog-to-digital converter, and the second output is connected to the first input of the second signal driver. The second input of the intermediate frequency amplifier, the fourth input of the digital adder and the first input of the first signal conditioning instrument are clock inputs. The central processor interface is connected to the first input-output of the first transceiver, the second input-output of which is connected to the first input-output of the second transceiver, and the third input-output is connected to the input-output of the first signal conditioner. The second input-output of the second transceiver is connected to the input-output of the second signal conditioner. The first output of the first signal conditioner is connected to the second input of the second signal conditioner, the second output is connected to the third input of the second signal conditioner, and the third, fourth, fifth, sixth and seventh outputs are connected respectively to the inputs of the first signal driver, first buffer, second signal driver, second buffer and third buffer. The first output of the second signal conditioner is connected to the input of the first transceiver, the second output is connected to the second input of the first signal conditioner, and the third, fourth, fifth, sixth and seventh outputs are connected respectively to the inputs of the fourth buffer, fifth buffer, level converter, sixth buffer and seventh buffer . The output of the first signal driver is connected to the fifth input of the digital adder. The outputs of the first buffer, the second signal driver, the second buffer, the third buffer, the fourth buffer, the fifth buffer, the level converter, the sixth buffer and the seventh buffer are respectively the outputs of the first, second, third, fourth, fifth, sixth, seventh, eighth and ninth control signals .

The essence of the claimed invention lies in the fact that the radar receiver contains n (n is an integer) of the receiving channels, the driver of the reference frequencies and the control device.

The drawing shows a functional diagram of a single-channel radar receiver with a control device, the remaining receiving channels have a similar structure.

A single-channel radar receiver with a control device contains a receiving channel, including an intermediate frequency amplifier (IFA) 1, analog-to-digital converter (ADC) 2, digital quadrature driver (DSC) 3, read-only memory (ROM) 4, digital heterodyning device (UTC) 5, adapter (A) 6, digital adder (DS) 7 and data transmitter (PD) 8. In addition, it contains a reference frequency driver (FOC) 9 and a control device consisting of a first transceiver (PP1) 10, a first signal former (FS 1) 11, the second transceiver (PP2) 12, the second signal conditioner (FS2) 13, the first signal driver (DS1) 14, the first buffer (B1) 15, the second signal driver (DS2) 16, the second buffer (B2) 17, the third buffer (B3) 18, fourth buffer (B4) 19, fifth buffer (B5) 20, level converter (PU) 21, sixth buffer (B6) 22 and seventh buffer (B7) 23.

The first input of the amplifier 1 is the input of the receiving channel. The output of the UPCH 1 is connected to the first input of the ADC 2, the first output of which is connected to the first input of the DPC 3. The output of the DSC 3 is connected to the first input of the UCH 5, the output of which is connected to the first input of the DS 7. The output of the DS 7 is connected to the first input of the PD 8, the output which is the output of the receive channel. The second output of the ADC 2 is synchronizing and connected to the second inputs of the DPC 3, UTsG 5, TsS 7 and PD 8. The output of the ROM 4 is connected to the third input of the UTsG 5. The first output of the adapter 6 is connected to the fourth input of the UTsG 5, and the second output is connected to the third the input of the CA 7. The control inputs and outputs of the UPCH 1 and adapter 6 are connected to the interface of the central processor (CPU interface). Input FOC 9 is the input of the reference signal Fop. The first output of the FOC 9 is connected to the second input of the ADC 2, and the second output is connected to the first input of the FS2 13. The second input of the IF 1, the fourth input of the DS 7 and the first input of the FS1 11 are inputs of the clock pulse TI.

The CPU interface is connected to the first input-output PP1 10, the second input-output of which is connected to the first input-output of PP2 12, and the third input-output is connected to the input-output of FS1 11. The second input-output of PP2 12 is connected to the input-output of FS2 13. The first output of FS1 11 is connected to the second input of FS2 13. The second output of FS1 11 is connected to the third input of FS2 13. The third, fourth, fifth, sixth and seventh outputs of FS1 11 are connected to the inputs of DS1 14, B1 15, DS2 16, B2 17 and B3 18, respectively. The first output of FS2 13 is connected to the control input PP1 10. The second output of FS2 13 is connected to the second input of FS1 11. The third, fourth, fifth, sixth and seventh outputs of FS2 13 are connected to inputs B4 19, B5 20, PU 21, B6 22 and B7 23 respectively. The output DS1 14 is connected to the fifth input of the DS 7. The outputs B1 15, DS2 16, B2 17, B3 18, B4 19, B5 20, PU 21, B6 22 and B7 23 are the outputs of the first (US1), second (US2), third (US3), fourth (US4), fifth (US5), sixth (US6), seventh (US7), eighth (US8) and ninth (US9) control signals, respectively.

Wherein:

US1 - impulse of blanking of the State Identification System;

US2 - a clock pulse of antenna control;

US3 - transmitter start pulse;

US4 - pulse blanking receiver;

US5 is the control pulse of the master simulator of the target simulator;

US6 - control pulse of the phase manipulator of the target simulator;

US7 - pulse control modes of the master oscillator;

US8 - pulse control master oscillator;

US9 - pulse control phase manipulator.

Consider the operation of a radar receiver with a control device on the example of the passage of the received signal through one receiving channel. Since the construction of the remaining receiving channels is identical to the first channel, the passage of the received signal through them will be similar.

From the high-frequency receiver, the input signal at the second intermediate frequency is fed to the first input of the amplifier 1. In this case, the amplifier 1 provides programmable gain and controlled frequency selection of the signals. From the output of the IF 1, the signal is fed to the first input of the ADC 2, the second input of which receives the sampling frequency signal from the first output of the FOC 9.

From the first output of the ADC 2, the signal is digitally supplied to the first input of the DPC 3. The clock signal from the second output of the ADC 2 is fed to the second inputs of the DSC 3, UTsG 5, TsS 7 and PD 8. From the output of the DSC 3 digital signals corresponding to real and imaginary the quadrature components of the signal are fed to the first input of the UTG 5, the third input of which receives correction factors from the output of the ROM 4. The frequency code of the digital local oscillator is fed to the fourth input of the UTG 5 from the first output of the adapter 6. After heterodyning, the signal goes to the first input of the DS 7, which th performs the summation of the samples of the signal on the interval of one element of range. The number of summarized samples, the delay in the start of the reception zone relative to the reference pulse (INO), the number of range elements in the reception zone, the delay in the start of the frame relative to the clock pulse of the TI (the number of transmitted INOs following after the TI) and the frame size (the number of INO in the frame) are determined by the corresponding codes received at the third input of the CA 7 from the second output of the adapter 6. Control commands UPCH 1 and adapter 6 are received from the central processor of the radar.

After summing the signal samples in DS 7, the total signal is divided by the number of summed samples (data normalization), after which the received signal is fed to the first input of PD 8, which provides the transmission of digital output to the secondary signal processing device of the radar station via serial LVDS (Low- Voltage Differential Signaling) to buses.

The control device generates control signals that ensure synchronization of the components of the radar. The control device is synchronized according to the clock pulse of the current transformer supplied to the first input of FS1 11, and through FS1 11 to the second input of FS2 13. From the second output of the FOC 9, the reference frequency comes to the first input of FS2 13, which is transmitted from the second output of FS2 13 to the second input FS1 11. On the CPU interface, control codes and commands are sent to PP1 10, which transmits them to PP2 12. PP1 10 and PP2 12 convert the serial code to parallel, followed by the transfer of control codes and commands to FS1 11 and FS2 13, respectively. FS1 11 and FS2 13 are built according to the circuit of pulse shapers on reversible counters, controlled by codes coming from PP1 10 and PP2 12. The formation of all synchronization signals of the radar is blocked in the absence of the ready signal, which is generated in FS2 13 and transmitted from its first output to the control input PP1 10.

FS1 11 generates the following signals:

- the reference pulse (INO) coming from the third output through DS1 14 to the fifth input of the CA 7;

- the blanking pulse of the State Identification System, coming from the fourth output through B1 15 to the output of the receiver US1;

- the clock antenna control pulse coming from the fifth output through DS2 16 to the output of the receiver US2;

- the transmitter trigger pulse coming from the sixth output through B2 17 to the output of the US3 receiver, while the pulse tied to the leading edge of the transmitter trigger pulse comes from the second output to the third input of FS2 13;

- pulse blanking receiver, coming from the seventh output through B3 18 to the output of the receiver US4.

FS2 13 generates the following signals:

- the control pulse of the master generator of the target simulator, coming from the third output through B4 19 to the output of the receiver US5;

- the control pulse of the phase manipulator of the target simulator, coming from the fourth output through B5 20 to the output of the US6 receiver;

- pulse control modes of the master oscillator coming from the fifth output through the PU 21 to the output of the receiver US7;

- the control pulse of the master oscillator coming from the sixth output through B6 22 to the output of the receiver US8;

- pulse control phase manipulator coming from the seventh output through B7 23 to the output of the receiver US9.

The radar receiver is controlled by the radar central processor via the Serial Management Interface (SMI) through the UPCH 1, the adapter 6 of the receive channel, and through the control device PP1 10 and PP2 12. Synchronization of the operation of the receiving channel is provided by the clock pulse TI coming from the synchronizer radar to the clock inputs of the IF 1, DS 7 and FS1 11, and the pulse of the origin of the INO, which is formed in the control device and coming from the output of the DS1 14 to the input of the reference of the DS 7.

The reference signal Fop to the input of the FOC 9 comes from the master radar. FOC 9 provides frequency filtering of the reference signal and the formation of differential signals of the sampling frequency with the levels and shape of the signals necessary for the operation of the ADC 2 of the receiving channel and FS1 11, FS2 13 of the control device.

To confirm the feasibility of implementing the technical solution, a prototype of a four-channel radar receiver with a control device with tactical and technical characteristics for a specific airborne radar station was made.

The control of the radar receiver from the central processor is carried out using the SMI interface. A control amplifier, a receiver channel adapter, and transceivers of the SMI interface of the control device are implemented on the FPGA (programmable logic integrated circuit) and provide the conversion of a serial code of control information received via the SMI interface into a parallel code of control signals. Multipliers, amplifiers and ADCs are selected from an industrially manufactured component base.

Digital processing of the signal coming from the ADC is organized on the basis of FPGA and provides the following operations: digital generation of quadrature of the input signal, filtering of high-frequency harmonics, digital heterodyning, summing of signal samples over the interval of one range element and dividing the result by the number of summations (data normalization) . Data is transmitted by the radar receiver through the LVDS data transmitter built into the FPGA. The control device is implemented on two FPGAs: the first transceiver and the first signal conditioner on the FPGA type EPM1270T144I5, the second transceiver and the second signal conditioner on the FPGA type EP2S15F484I4. Buffers, signal drivers, and a level converter are implemented on integrated circuits.

To reduce the weight and size characteristics of the radar receiver, the analog parts (UPCH) of the two channels are made in a single module of the Euromechanics-3U standard, while the SMI interface transceiver is made on one FPGA. Also, the digital parts of two channels are made in a single module, while the DPC, UTsG, ROM, TsS, PD and the adapter for both channels are made on the same FPGA. In separate modules, a reference frequency driver and a control device are made. Thus, a fully four-channel radar receiver with a control device in the performance of Euromechanics of frame size 1ATR Short consists of six modules of the Euromechanics-3U standard. Additionally, it can be used in conjunction with the central processor module. The power source is made according to the standard scheme, depending on the requirements for primary power systems.

The obtained characteristics of a prototype radar receiver with a control device confirm the achievement of the technical result of the claimed invention.

Claims (1)

A radar receiver with a control device containing n (n is an integer) of receiving channels and a reference frequency driver, wherein each receiving channel includes an intermediate frequency amplifier, an analog-to-digital converter, a digital quadrature driver, read-only memory, a digital heterodyning device, an adapter, digital adder and data transmitter, the first input of the intermediate frequency amplifier is the input of the receiving channel, the output of the intermediate frequency amplifier is connected to the first input analog-to-digital converter, the first output of which is connected to the first input of the digital quadrature driver, the output of the digital quadrature driver is connected to the first input of the digital heterodyning device, the output of which is connected to the first input of the digital adder, the output of the digital adder is connected to the first input of the data transmitter, the output of which is the output of the receiving channel, the second output of the analog-to-digital converter is connected to the second inputs of the digital quadrature driver, the digital heterodyning, digital adder and data transmitter, the output of read-only memory is connected to the third input of the digital heterodyning device, the first output of the adapter is connected to the fourth input of the digital heterodyning device, and the second output is connected to the third input of the digital adder, the inputs and outputs of the intermediate frequency amplifier and adapter are connected with the interface of the central processor, the input of the reference frequency driver is the input of the reference signal, the first output of the reference driver This is connected to the second input of the analog-to-digital converter, the second input of the intermediate-frequency amplifier and the fourth input of the digital adder are clock inputs, characterized in that a control device is introduced into it, comprising a first transceiver, a first signal conditioner, a second transceiver, and a second signal conditioner, first, second, third, fourth, fifth, sixth and seventh buffers, first and second signal drivers, level converter, while the CPU interface dinene with the first input-output of the first transceiver, the second input-output of which is connected to the first input-output of the second transceiver, and the third input-output connected to the input-output of the first signal conditioner, the second input-output of the second transceiver connected to the input-output of the second driver signals, the first input of the first signal conditioner is a clock input, the first output of the first signal conditioner is connected to the second input of the second signal conditioner, the second output is connected to the third the input of the second signal conditioner, and the third, fourth, fifth, sixth and seventh outputs of the first signal conditioner are connected respectively to the inputs of the first signal driver, the first buffer, the second signal driver, the second buffer and the third buffer, the first input of the second signal conditioner is connected to the second output of the signal conditioner reference frequencies, the first output of the second signal conditioner is connected to the input of the first transceiver, the second output is connected to the second input of the first signal conditioner, and the third, four the fifth, fifth, sixth and seventh outputs of the second signal conditioner are connected respectively to the inputs of the fourth buffer, fifth buffer, level converter, sixth buffer and seventh buffer, the output of the first signal driver is connected to the fifth input of the digital adder, the outputs of the first buffer, second signal driver, second the buffer, the third buffer, the fourth buffer, the fifth buffer, level converter, the sixth buffer and the seventh buffer are respectively the outputs of the first, second, third, fourth, fifth, sixth, seventh second, eighth and ninth control signals.