RU2495449C2 - Apparatus for forming active phased antenna array beam pattern - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: apparatus for forming the beam pattern of a active phased antenna arrays has N identical channels, each having series-connected intermediate frequency amplifiers, the input of which is the channel input, an analogue-to-digital converter, a switch, the second input of which is connected to the output of random-access memory, a digital heterodyne unit, a multiplier, the second input of which is connected to read only memory, and the quadrature output of which is the channel output. Outputs of all N channels are connected to inputs of a digital adder, the output of which is connected to series-connected digital filter, interfacing unit and optical transmitter, the output of which is the output of the apparatus.

EFFECT: broader functional capabilities of the apparatus owing to a wider dynamic range, enabling debugging and control of the operating algorithm of the apparatus and longer transmission range of the generated data.

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Description

The invention relates to antenna technology and is intended to form a radiation pattern (LH) in a connected or radar active phased array antenna (AFAR).

Known radio receiver of a coherent radar station [RF Patent 2189054 from 07.28.2000], containing a local oscillator and a coherent receiver with a digital output, N (N is an integer) of the reception channels, each consisting of an inputted analog adder, a coherent receiver with a digital output and an introduced phase shifter, and in each receiving channel, the input of the radio receiver is connected to the first input of the introduced analog adder, the second input of the analog adder is connected to the output of the introduced phase shifter, the input of which connected to the output of the local oscillator, the output of the analog adder is connected to the first input of the coherent receiver with a digital output, the second input of the coherent receiver with the digital output of each channel is connected in parallel with the output of the local oscillator, the first output of the coherent receiver with the digital output of each channel is connected to the same input of the first digital adder, the second output of the coherent receiver with a digital output of each channel is connected to the same input of the second digital adder, and the output of the first digital adder is is the first output of the radio receiver and the output of the second digital adder is the second output of the radio receiver.

Each coherent receiver with a digital output consists of a radio frequency amplifier, the output of which is connected in parallel to the inputs of two synchronous frequency converters, each of the outputs of which, respectively, is connected to the input of a corresponding low-pass filter, the output of which is connected to the input of a corresponding analog-to-digital converter, the output of which is the real or, accordingly, imaginary part of the output signal of the receiver, and the output of the local oscillator is connected to the input of the voltage reference of the second sync the converter and the input of the phase shifter, the output of which is connected to the input of the reference voltage of the second synchronous converter.

However, the known device has a low dynamic range of analog-to-digital conversion, since a quadrature analog-to-digital conversion is used, with obtaining quadratures in an analogous manner. With this method of obtaining quadrature in practice, it is impossible to achieve high identity characteristics of analog quadrature, which reduces the dynamic range of the device.

The closest analogue in essence to the invention is a digital heterodyning radar receiver [RF patent 2225623 from 09.17.2002], taken as a prototype, which contains N channels, each of which includes an intermediate frequency amplifier (IF), two synchronous converters, two lower filters frequencies (low-pass filter), two analog-to-digital converters (ADCs), a digital heterodyning unit, read-only memory (ROM) and a phase shifter, in addition, the device includes a reference signal shaper, two digital sums ora, crystal oscillator, parallel information highway.

The prototype has several significant disadvantages:

1. The prototype does not provide a coherent analog-to-digital conversion of the input signals, since the ADC blocks are clocked by built-in generators that do not have any connections between themselves. Thus, due to the lack of synchronization of the moments of taking samples of the received signals in different processing channels, the prototype has a large error of the moments of taking samples in frequency and phase. We estimate this error under the assumption that each ADC unit has a built-in crystal oscillator of the sampling frequency signal. It is known that quartz oscillators have a frequency instability of at least 15 · 10 ^-6 [Quartz oscillators, filters, resonators, crystal elements, Morion OJSC. 2009. - p. 81-83].

As follows from the description of the prototype, low-pass filters have a band of 3.2 MHz. That is, in accordance with the Kotelnikov theory, the signal samples should be taken with a frequency of at least two times greater, that is, 6.4 MHz. Random changes in the frequency of crystal oscillators in different channels of the prototype will be equal to 6.4 · 10 ⁶ · 10 · 10 ^-6 = 64 Hz. Thus, the difference in the sampling frequencies of the input signal in different processing channels is a random variable and can reach 64 Hz. The phase error can reach 360 °. This significantly increases the error in the formation of MDs in the form of an increase in the side lobes of the MD and the displacement of the maximum of the main lobe of the MD relative to the calculated one.

2. The prototype has a low dynamic range of analog-to-digital conversion, since a quadrature analog-to-digital conversion is used to obtain quadratures in an analogous way, while the frequency of the input signal is converted to zero intermediate frequency (IF) using the reference signal and two synchronous converters, using 90 ° phase shifter simultaneously forms analog quadrature components of the input signal, which are filtered by the low-pass filter and converted into digital readings using the ADC. This circuit is characterized by a low dynamic range of analog-to-digital conversion due to the inability to achieve identical characteristics of synchronous converters and low-pass filters in a wide frequency band and with changes in ambient temperature. In accordance with [Digital filters and signal processing devices on integrated circuits / F.B. Vysotsky, V.I. Alekseev and others. M.: Radio and communications. 1987. - p.24] to achieve a dynamic range in discrete spurious components of at least 40 dB, it is necessary to have deviations of the low-pass filter and converter characteristics from ideal ones of at least 1%, which is difficult to put into practice in the operating frequency range.

3. The prototype has limited accuracy in setting the phase relations in the channels, since it ensures the formation of DNs only by analog phase shifters. The receiver receives analog signals, and the receiver only sums the received signals. That is, analog phase shifters installed in the radar path in front of the receiver are used to form the beam. Analog phase shifters provide a pitch of at least 5.625 ° [Design of phased array antennas / Ed. DI. Voskresensky. M .: Radio engineering. 2003. - p. 503-531] and are bulky devices whose parameters depend on the ambient temperature. However, in modern radars, the formation of MDs with a smaller step is required, which can only be provided by digital methods of forming the MD.

4. The prototype lacks the ability to control the health of the device and debug it without using external signal sources. However, in the process of setting up the device and its operation, it is necessary to check its operability and the correct operation of all channels. The prototype has a crystal oscillator, the signal from which is fed to all channels of the device. It can be used as a source of control signal for a rough assessment of the health of the device. However, to check the operability of the operation algorithm as part of the AFAR, it is necessary to apply signals with a phase shift relative to each other to the different receiving channels as they arrive at the antenna array. In this case, the phase shift is determined by the direction to the signal source.

5. The prototype ensures the transmission of generated data only to a limited distance, since a parallel interface is used to output the data. This makes it difficult to construct MDs for multi-element headlamps in the ranges of ultrashort waves (VHF) and short waves (KB) with large geometric dimensions, since parallel interfaces are not designed to transmit data over distances exceeding several tens of centimeters, however, to construct devices for the formation of multi-element headlights the ability to transfer data between blocks over longer distances, at least a dozen meters with high noise immunity.

The aim of the creation of the invention is to expand the functionality of the device by increasing the dynamic range, providing the ability to control the health of the device without using external signal sources and increasing the transmission range of the generated data.

To achieve this goal, it is proposed a device for generating an AFAR detector containing a digital adder, a parallel information line and N receiving channels, each of which includes a ROM and a series-connected amplifier, an analog-digital converter, and a digital heterodyning unit, while the parallel information line is connected to the ROM control input .

According to the invention, a digital filter is introduced into the device, the input of which is connected to the output of the digital adder, an interface unit, the input of which is connected to the output of the digital filter, an optical transmitter whose input is connected to the output of the interface unit, and the output is the output of the device, an optical receiver, the input of which is the control input of the device, the control unit, the input of which is connected to the output of the optical receiver, the synchronization input is the synchronization input of the device, and the output is connected to the parallel line information, a power divider, the input of which is the input of the sampling frequency, and N outputs are connected to the ADC clock inputs in all N channels, a switch is inserted into each receiving channel of the device, the input of which is connected to the ADC output, and the output is connected to the input of the digital heterodyning unit, RAM, the input of which is connected to the ADC output, the output is connected to the second input of the switch, and the control input is connected to the parallel information highway, a multiplier, the first input of which is connected to the output of the digital block eterodinirovaniya, the second input of which is connected to the output of the ROM, and the output is the output of the receiving channel and connected to the input of the digital adder, the control inputs of the IF amplifier and a switch connected to the parallel line information.

A comparative analysis of the claimed device and prototype shows that the claimed device is characterized in that:

- in the prototype, the timing of the moments of sampling in the ADC of different channels is carried out asynchronously under the control of the clock generators built into the ADC blocks, which do not have any connections between themselves. In contrast, in the proposed device, the formation of samples of the received signal in different channels is performed synchronously at the same time under the control of a sampling signal with a frequency Fd coming to the device from the outside; for this, a signal power divider Fd and communication lines from power divider for each ADC;

- in the prototype, in each channel, the quadrature samples of the input signal are generated in an analog way using a phase shifter, two synchronous converters, two low-pass filters and two ADCs. In contrast, the proposed device in each channel uses one ADC, and the formation of quadrature samples of the input signal is performed digitally in the digital local oscillator unit, for this two multipliers are introduced into the digital local oscillator unit;

- in the proposed device in each channel introduced RAM and a switch, providing the ability to record samples of the input signal or a control sequence of numbers and feed them to the input of the digital local oscillator block;

- the prototype does not provide a change in the phase relationships of the signals in different channels and the formation of the pattern, for the formation of the pattern are analog phase shifters that are not part of the device and are installed in the receiving path in front of the prototype. In contrast, in the proposed device, a multiplier is introduced into each channel, and the ROM is used to store a table of values of weight coefficients, which makes it possible to change the phase relationships in the channels;

- in the prototype, the transfer of generated data is carried out via a parallel interface. In contrast, in the proposed device, the transmission of generated data is carried out via a fiber optic communication line (FOCL) with serial data transmission, which is ensured by the use of an optical transmitter and a pairing unit;

- in the prototype, device control is carried out along a parallel line. In contrast, in the proposed device, the nodes are controlled by control commands received via the fiber optic link with serial data transmission, the nodes are controlled by the built-in control unit; for this, an optical receiver, a control unit, and control lines from the control unit to the nodes are introduced into the device.

The combination of distinctive features and properties of the proposed device for the formation of AF APA from the literature is not known, therefore, it meets the criteria of novelty and inventive step.

Figure 1 shows a diagram of a device for forming a day AFAR.

Figure 2 shows a block diagram of a digital local oscillator.

Figure 3 shows the signal reception diagram of the antenna array.

The device for forming an AFAR detector (Fig. 1) consists of N identical channels A ₁ ... A _N , each i-th of which, i = 1 ... N, contains a series-connected IF 1, whose input is the input of the i-th channel, ADC 2 , a switch 3, to the second input of which the output of RAM 4 is connected, a digital local oscillator unit 5, a multiplier 6, to the second input of which a ROM 7 is connected, and whose output is the channel output.

The outputs of all N channels are connected to the inputs 1 ... N of the digital adder 8, the output of which is connected to a digital filter (DF) 9, the output of which is connected to the interface unit 10, the output of which is connected to the optical transmitter 11, the output of which is the output of the device.

The control input of the device is the input of the optical receiver 12, the output of which is connected to the control input of the control unit 13, the control output of which is connected via the parallel information line to the control inputs of the amplifier 1, RAM 4, switch 3, digital heterodyning unit 5 and ROM 7 of all channels, and The sync input is the sync input of the device.

The input of the sampling frequency signal is the input of the power divider 14, the N outputs of which are connected to the clock inputs of the ADC 2 in each of the N channels of the device.

The digital heterodyning unit 5 (Fig. 2) includes: a first multiplier 15, the first input of which is the input of the unit, the in-phase output of the digital local oscillator 16 is connected to the second input, and the output is connected to the input of the second DF 17, the output of which is the in-phase part of the output of the unit , the second multiplier 18, the first input of which is combined with the first input of the first multiplier 15, the quadrature output of the digital local oscillator 16 is connected to the second input, and the output is connected to the input of the third DF 19, the output of which is the quadrature part ode block.

ADC 2 is designed to convert the received signal into digital samples. The number of bits of the ADC should be at least 12, which provides a signal-to-noise ratio in the ideal case of 73.94 dB [Analog-to-Digital Conversion / Ed. W. Kester. - M .: Technosphere. 2007 - p. 103]. In real ADCs, the signal-to-noise ratio at the output is slightly less. For example, for an ADC type ADS6128 manufactured by Texas Instruments, the signal-to-noise ratio is 70.1 dB, while the dynamic range of the discrete components is at least 81 dB [14/12-Bit, 250/210 MSPS ADCs With DDR LVDS and Parallel CMOS Outputs. Texas Instruments. 2009].

The digital adder 8 is intended for quadrature summation of the signal samples coming from the outputs of the multipliers 6 of all N channels and can be performed on the FPGA in accordance with the structural diagram given in [Digital radio receiving systems. Ed. M.I. Zhodzishsky. M .: Radio and communication. 1990. - Fig. 2.13, p. 51].

RAM 4 is designed to store samples of the control signal and can be performed in accordance with the scheme given in [Digital filters and signal processing devices on integrated circuits / FB Vysotsky, V.I. Alekseev et al. M .: Radio and communications. 1987. - p. 55-56].

ROM 7 is designed to store the weight coefficients W (ff) used to form the DN and can be performed in accordance with the scheme given in [Digital filters and signal processing devices on integrated circuits / F.B. Vysotsky, V.I. Alekseev et al. M .: Radio and communications. 1987. - p. 105].

The power divider 14 provides branching of the sampling signal, Fd supplied to the input of the device, into N outputs. It can be performed, for example, on power dividers manufactured by Mini-Circuits [Mini-Circuits. IF / RF Components Guide. 2007]. Since the company produces dividers with a different number of channels from 2 to 48, the specific types of elements used are determined by the number of channels N in the AFAR. If N exceeds 48, then it is necessary to use a serial branching of the input signal to achieve the required number of channels. The implementation of multi-channel DM on 64 channels is also described in [Design of phased antenna arrays. Ed. DI. Voskresensky. M .: Radio engineering. 2003, pp. 550-551].

Digital local oscillator 16 is designed to generate a quadrature digital signal with which the conversion of the samples of the received signal into a quadrature form and the conversion of its frequency to zero IF can be performed on the basis of a counter, adder and ROM, in which the values of the quadrature components of the local oscillator signal are recorded in accordance with the scheme given in [L.A. Belov Synthesizers of frequencies and signals - M .: Sainz-press, 2002. - Fig. 31].

Multipliers 6, 15 and 18 can be made on the FPGA in accordance with the structural diagram given in [Digital radio receiving systems. Ed. M.I. Zhodzishsky. M .: Radio and communication. 1990 - Fig. 2.19, p. 57].

The second 17 and third 19 digital filters are designed to filter and thin out (decimate) the received signal and are based on cascade integrators - comb filters [Lyons R. Digital signal processing. M .: Binom. 2006. - pp. 397-409]. In foreign literature, these filters are usually called CIC filters.

Digital local oscillator 16, first 15 and second 18 multipliers and second 17 and third 19 digital filters, depending on the beats sampling frequency used in the device, can be performed using an AD6620 chip manufactured by Analog Devices [AD6620. 67 MSPS Digital Receive Signal Processor. Analog Devices. 2001] or on the FPGA.

DF 9 is designed to correct the end-to-end frequency response generated by the second 17 and third 19 digital filters and can be performed, for example, on microcircuits such as HSP43220, HSP43168 manufactured by Harris Semiconductor [Digital Signal Processing Databook. Harris Semiconductor. 1994, pp. 3-35, 3-60] or on the FPGA.

The interface unit 10 is designed to convert parallel codes of samples received from the digital filter 9 into a serial code and their subsequent transmission through an optical transmitter. The interface unit 10 can be performed on the FPGA, for example, on the basis of a shift register or a two-port FIFO buffer in accordance with [Ugryumov E. Digital circuitry. St. Petersburg: BHV-Petersburg. 2004 - Fig. 4.7], which is written to in parallel code, and read in sequential code.

The optical receiver 12 and the optical transmitter 11 can be implemented, for example, on an optical transceiver type AFCT-5944 manufactured by Avago Technologies [Avagotech.com website].

The control unit 13 is designed to receive control commands received via the fiber optic link through the optical receiver 12 and set the parameters of the amplifier 1, RAM 4, digital heterodyne unit 5, switch 3 and ROM 7 and can be performed on the basis of a microprocessor, the structure is similar to that given in [Digital filters and signal processing devices on integrated circuits / F.B.Vysotsky, V.I. Alekseev et al. M .: Radio and communications. 1987 - p. 126], based on the microprocessor structure described in [Ugryumov E. Digital circuitry. St. Petersburg: BHV-Petersburg. 2004 - Fig. 5.1] or on the FPGA.

The device for the formation of DN AFAR works as follows.

Consider the case when the AFAR in which the proposed device is used is made on the basis of a linear antenna array, in which the antenna elements (AE) are located in one line at a distance d = λ / 2 from each other (Fig. 3), where λ = c / Fвx - wavelength of the received signal,

Fвx - input signal frequency,

c is the speed of light.

If the direction to the signal source is at an angle relative to the perpendicular to the AFAR plane, then the signal to different AEs of the antenna array (are not included in the proposed device) will come with a different phase. The relative phase of the received signal from this source at the i-th input of the proposed device, i = 1 ... N, has the form:

$${\phi }_i=k(i-\mathrm{one})d\sin (\theta ),(\mathrm{one})$$

where k = 360 ° / λ is the phase constant of space;

θ is the direction to the signal source.

In order to form a maximum of the directivity pattern (LF) of the linear array in the direction of the signal source, it is necessary to sum the signals from the outputs of the antenna elements after equalizing the moments of their arrival by phase shift by the value (1).

When a signal arrives at the device’s inputs, the received signal in each channel is amplified and filtered by frequency in UPCH 1. The band-pass filter in UPCH 1 should ensure that there is no “overlap” of the signal during analog-to-digital conversion, that is, the passband ΔF should be no less than two times less than the sampling frequency ΔF <Fd / 2. [Poberezhsky E.S. Digital radio receivers. - M .: Radio and communication. 1987 - p. 42]

и сдвигаются по частоте на нулевую ПЧ путем перемножения в первом 15 и втором 18 перемножителях с квадратурными гармоническими сигналами цифрового гетеродина 16. Во втором 17 и третьем 19 ЦФ нижних частот производится фильтрация преобразованного сигнала, полоса пропускания этих фильтров равна половине ширины спектра принимаемого сигнала.After amplification and filtering, the signal is converted into a sequence of samples S _i (k) (here k is the number of samples in the sequence) in ADC 2, then the samples pass through switch 3 to digital heterodyning unit 5, where the actual samples are converted into a sequence of complex (quadrature) samples $${\dot{S}}_i(k)$$

and frequency shifted to zero IF by multiplying in the first 15 and second 18 multipliers with quadrature harmonic signals of the digital local oscillator 16. In the second 17 and third 19 low-frequency filters, the converted signal is filtered, the bandwidth of these filters is equal to half the width of the spectrum of the received signal.

, хранящийся в ПЗУ 7, определяющий фазовый сдвиг сигнала, поступающего на i-й вход устройства. Выбор коэффициента определяется адресом, поступающим от блока управления на ПЗУ 7. Отсчеты с выходов всех N каналов суммируются в цифровом сумматоре 8. Последовательность отсчетов сформированного луча с угловыми координатами θ имеет вид:To form the maximum of the pattern in the θ direction, the obtained samples are multiplied in the multiplier 6 by the complex weight coefficient $${\dot{W}}_i(\theta \text{A.})$$

stored in ROM 7, which determines the phase shift of the signal received at the i-th input of the device. The selection of the coefficient is determined by the address coming from the control unit to the ROM 7. The samples from the outputs of all N channels are summed up in the digital adder 8. The sequence of samples of the generated beam with angular coordinates θ has the form:

$${\dot{D}}_k(\theta \text{A.},\varphi )={\displaystyle \sum _{i=\mathrm{one}}^N{\dot{S}}_i(k)*{\dot{W}}_i(\theta \text{A.})}(2)$$

After summing, the signal is filtered in the digital filter 9, providing the desired shape of the frequency response of the receiving channels of the device. Next, the parallel sample code is converted to a serial code in the interface unit 10. The resulting sample stream is transmitted to the optical transmitter 11 and transmitted via the FOCL to the post-processing device (not shown in FIG. 1).

In the control mode, the device uses the samples previously recorded in RAM 4, while the input of the digital heterodyning unit 5 through the switch 3 is connected to the RAM 4. The signal samples in RAM 4 can be recorded in advance as samples of the real signal from the output of the ADC 2 or as calculated values calculated using a specially designed program. Reading the signal samples from the RAM 4 memory, you can simulate any location of the signal source relative to the antenna array and the presence of jamming signals. This mode is used to check the operability of the device and debug its software.

The control commands for setting the modes and parameters of the nodes of the proposed device are received via the fiber optic link to the optical receiver 12 and then to the control input of the control unit 13.

The proposed device has three modes of operation:

- work with the received signal when the formation of the beam is made using the signals from the antenna elements of the antenna array;

- recording samples of the signal in RAM 4, and recording samples of real signals can be performed simultaneously with the first mode;

- control mode, when the formation of the pattern using samples of signals recorded previously in RAM 4.

In the proposed device, the following parameters are set: the direction of the maximum DN in, the band of the received signal ΔF, the tuning frequency F of the signal θ within the passband of the UHF 1, the transmission coefficient K UHF 1. After receiving the command, the parameters of the device nodes are set by transmitting codes from the control unit 13.

The transfer coefficient is set in UPCH 1, in the digital heterodyning unit 5, the frequency of the digital local oscillator 16 is equal to the center frequency of the spectrum of the received signal F and the passband is equal to ΔF / 2 in the digital filter 9, the second 17 and the third 19 digital filters, and in each i- ROM volume 7 (i = 1 ... N) sets the address of the cells in which the quadrature values of the i-th weight coefficient for the angle θ are recorded.

If several samples of the proposed device are used in the AFAR, the Sync signal used to synchronize the control unit 13 is used to synchronize their operation.

The Sync signal is a video pulse generated by external control devices (not shown in FIG. 1), indicating the moment of the beginning of the device operation period to ensure synchronous operation of several identical devices.

When using the proposed device for the formation of MDs in a continuous mode, the Sync signal serves to:

- synchronization of simultaneous switching of parameters in all devices included in the antenna array,

- in the mode of recording samples of the signal in RAM 4 to start the process of recording samples in RAM 4,

- in control mode to start the process of reading from RAM 4.

When using the proposed device for generating radiation patterns in pulsed radars, it is necessary to include the reception gate length ΔT in the parameter list, and the Sync signal will be used to synchronize the beginning of the reception gate in all devices included in the antenna array.

To confirm the feasibility of implementing the technical solution, a mock-up of the device for forming the DN in the form of a printed circuit board with N = S was made, tests of which confirmed its high technical characteristics.

Compared with the prototype, the proposed device has higher parameters than the prototype:

- the signal-to-noise ratio at the output of the digital part of each channel is not less than 70 dB, the dynamic range by discrete components is not less than 81 dB due to the use of the digital method for producing quadrature signal components instead of the analog method in the prototype,

- it is possible to control the operability of the device without using external signal sources through the use of RAM, in which it is possible to store signal samples;

- the transmission range of the generated data has been increased to several kilometers due to the use of FOCL, while in the prototype the parallel bus provides data transmission at distances not exceeding several tens of centimeters.

Claims (1)

A device for generating a radiation pattern of an active phased antenna array containing a digital adder, a parallel information line and N receiving channels, each of which includes a permanent storage device and a series-connected intermediate frequency amplifier, an analog-to-digital converter, a digital heterodyning unit, while information is connected to the control input of a read-only memory device, characterized in that digital the second filter, the input of which is connected to the output of the digital adder, the interface unit, the input of which is connected to the output of the digital filter, the optical transmitter, the input of which is connected to the output of the interface unit, and the output is the output of the device, the optical receiver, the input of which is the control input of the device, unit control, the input of which is connected to the output of the optical receiver, the synchronization input is the synchronization input of the device, and the output is connected to the parallel information highway, power divider, the input of which is the input of the sampling frequency, and N outputs are connected to the clock inputs of analog-to-digital converters in all N channels, a switch is inserted into each receiving channel of the device, the input of which is connected to the output of the analog-to-digital converter, and the output is connected to the input of the digital heterodyning unit, operational a storage device, the input of which is connected to the output of the analog-to-digital converter, the output is connected to the second input of the switch, and the control input is connected to the parallel ation, a multiplier, a first input coupled to the output of the digital heterodyne technique, the second input of which is connected to the output of a read only memory, and the output is the output of the receiving channel and connected to the input of the digital adder, the control inputs of the intermediate frequency amplifier and a switch connected to a line parallel to the information.

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