RU2514789C1 - Rs flip-flop with multidigit internal signal presentation - Google Patents

Abstract

FIELD: physics, computer engineering.

SUBSTANCE: invention relates to computer engineering and automation, and can be used in different digital structures, automatic control and information transmission systems. The device has R and S inputs, output transistors, an auxiliary voltage source, inverting amplifiers in form of current mirrors, current outputs, reference current sources, power supply buses and additional transistors.

EFFECT: high speed of operation and creating an element base for computing devices operating on multidigit linear algebra principles.

2 cl, 16 dwg

Description

The present invention relates to the field of computer engineering, automation and can be used in various digital structures and systems for automatic control, information transfer, etc.

In various computing and control systems, devices based on RS-flip-flops are widely used, which have two states depending on potential signals at the R or S-inputs [1-20]. The input and output signals in classical triggers are high or low potentials corresponding to logical “1” or logical “0” of Boolean algebra.

In [21], as well as in the monographs of the co-author of this application [22-23], it was shown that Boolean algebra is a special case of a more general linear algebra, the practical implementation of which in the structure of computing and logical devices of automation of a new generation requires the creation of a special element base implemented on based on logic with a multi-valued internal representation of signals, in which the current quantum I ₀ is the equivalent of a standard logical signal. The inventive device relates to this type of computing device.

The closest prototype of the claimed device is an RS-trigger presented in patent RU No. 2119716. It contains (Fig. 1) R (1) and S (2) inputs, output transistors 3 and 4, the bases of which are connected to the auxiliary voltage source 5, the first 6 and second 7 inverting amplifiers with the corresponding first 8 and second 9 current outputs, the first 10 source of reference current, the first 11 and second 12 bus power source.

A significant drawback of the well-known RS-trigger is that, using potential binary signals, it has a complicated communication structure, non-linearity of the operating modes of elements and the criticality of the structure parameters of the PS, as well as the input signals, which ultimately leads to a decrease in its speed.

The main objective of the invention is to create a device in which the internal conversion of information is carried out in a multi-valued current signal form, determined by the state of the input current signals. Ultimately, this allows you to improve performance and create the element base of computing devices operating on the principles of multi-valued linear algebra [22-23].

The problem is solved in that in the RS-trigger with a multi-valued internal representation of the signals (Fig. 1), containing R (1) and S (2) inputs, output transistors 3 and 4, the bases of which are connected to the auxiliary voltage source 5, the first 6 and the second 7 inverting amplifiers with the corresponding first 8 and second 9 current outputs, the first 10 reference current source, the first 11 and second 12 power supply buses, new elements and communications are provided - the first 6 and second 7 inverting amplifiers use the corresponding first 6 and at 7 current mirrors, matched with the first 11 bus of the power source, the input of the first 6 current mirrors is connected to the collector of the first 3 output transistor, the auxiliary current output 13 of the first 6 current mirrors is connected to the emitter of the second 4 output transistor and S-input (2) of the trigger, and also through the second 14, the reference current source is connected to the second 12 bus of the power source, the input of the second 7 current mirror is connected to the collector of the second 4 output transistor, the auxiliary current output 15 of the second 7 current mirror is connected to by the mitter of the first 4 output transistor and the R-input (1) of the trigger, as well as through the first 10, the reference current source is connected to the second 12 bus of the power source, and the current outputs 8 and 9 of the first 6 and second 7 are used as antiphase current outputs of the RS trigger current mirrors.

Scheme RS-trigger prototype shown in the drawing of figure 1. The drawing of figure 2 presents a diagram of the inventive device in accordance with claims 1 and 2 of the claims for the case when the first 3 and second 4 output transistors have an n-pn type of conductivity.

The drawing of Fig. 3 shows a diagram of the inventive device in accordance with claim 1 for the case when the first 3 and second 4 output transistors have a pnp type of conductivity (examples of constructing the first 6 and second 7 current mirrors are given in the drawing of FIG. .9).

The drawing of Fig. 4 shows a diagram of the RS-flip-flop of Fig. 3 on ideal elements in a Cadence environment on SiGe models of non-integrated transistors.

The drawing of figure 5 shows the static mode of the RS-trigger of figure 4 with the input current at the S input I7 = 500 μA.

The drawing of Fig.6 shows the timing diagram of the input and output currents of the RS-trigger of Fig.4.

The drawing of Fig.7 shows a timing diagram of the delays in the output current signal.

The drawing of Fig. 8 shows the input logic for constructing an RSC trigger based on the inventive RS trigger.

The drawing of Fig.9 shows a diagram of an RSC trigger in a MicroCap environment and the functional designations of its outputs on the StageT block with the input logic of Fig.8 RS trigger of Fig.3.

The drawing of Fig. 10 shows a functional diagram and connection of the conclusions of the RS-flip-flop with the power supply unit "Supply" (Fig. 11), an input unit for converting potential signals to current "Input" (Fig. 12) and the RS-trigger "StageT" (Fig. .3).

The drawing of Fig. 11 shows a particular embodiment of building potential bias circuits and supply voltages of the RS-flip-flop in the form of a "Supply" power supply.

In the drawing of Fig.12 shows the block "Input" for the formation of the input current signals of the RS-trigger of Fig.3 from potential signals. In most cases, the “Input” block may be missing.

The drawing of Fig.13 shows the timing diagrams of the input and output current signals of a single-stage RSC-trigger of Fig.9 (sequence of graphs: currents S, R, C, Q1, Q2).

The drawing of Fig.14 shows a two-stage RSC-trigger, implemented on the basis of the inventive RS trigger.

The drawing of Fig.15 shows the timing diagrams of the input and output current signals of the two-stage trigger of Fig.14 (sequence of graphs: currents S, R, C, Q1_1, Q2_1, Ql_2, Q2_2).

In the drawing of Fig.16 shows an embodiment of the construction of a T-trigger based on the proposed RS-trigger of Fig.3.

RS-trigger with a multi-valued internal representation of the signals of figure 2 contains R (1) and S (2) inputs, output transistors 3 and 4, the bases of which are connected to the auxiliary voltage source 5, the first 6 and second 7 inverting amplifiers with the corresponding first 8 and the second 9 current outputs, the first 10 source of reference current, the first 11 and second 12 bus power source. As the first 6 and second 7 inverting amplifiers, the corresponding first 6 and second 7 current mirrors are used, matched with the first 11 bus of the power supply, the input of the first 6 current mirror is connected to the collector of the first 3 output transistor, the auxiliary current output 13 of the first 6 current mirror is connected to the emitter of the second 4 output transistor and S-input (2) of the trigger, as well as through the second 14, the reference current source is connected to the second 12 bus of the power source, the input of the second 7 current mirror is connected to the collector w of the next 4 output transistor, the auxiliary current output 15 of the second 7 current mirror is connected to the emitter of the first 4 output transistor and the R-input (1) of the trigger, and also through the first 10 the reference current source is connected to the second 12 bus of the power source, moreover, as antiphase current RS-flip-flop outputs use current outputs 8 and 9 of the first 6 and second 7 current mirrors.

In addition, in the drawing of figure 2, in accordance with paragraph 2 of the claims, the first 16 and second 17 additional transistors are introduced into the circuit, the bases of which are connected to the auxiliary voltage source 5, the emitters are connected to the emitters of the corresponding first 3 and second 4 output transistors , and the collectors are connected with the corresponding auxiliary current outputs 18 and 19 of the device.

As the first 6 and second 7 current mirrors, the authors recommend using classic circuits, examples of which are given in the drawing of Fig. 8 (elements 26, 27) and the drawing of Fig. 9. The required current transfer coefficient of the data of the functional units (Ko = 1 ÷ 2, FIG. 2, FIG. 3) is established by choosing the appropriate emitter transition areas of the applied transistors.

The circuit of figure 3 corresponds to claim 1 of the claims, but is implemented on pnp transistors 3 and 4.

The two-terminal circuits 20 and 21 model the load properties of the RS-flip-flop at outputs 8 and 9. The input logic of the RS-flip-flop of Fig. 8 is implemented on transistors 22, 23, 24, 25, 26, 27. The input logic signal of this logic is fed to input 28, and the clock signal is at input 29. To establish a static logic mode, input 30 is used, to which a current quantum I ₀ is applied.

Consider the work of the proposed circuit RS-trigger figure 3.

As you know, there are two trigger modes:

- the mode of setting the trigger in a certain state;

- state storage mode.

The state storage mode is characterized by the absence of flowing current quanta at its inputs Bx.R (1) and Bx.S (2). If in the “logical 1” state, for example, the transistor 3 is open, then a current equal to the current quantum specified by the reference current source 10 flows in its collector circuit. In this case, the first 6 current mirror, through the auxiliary current output 13, selects the current quantum of the reference source current 14. The collector current of the transistor 4 is absent, therefore, there is no current in the second 7 current mirror. Therefore, its auxiliary output 15 does not affect the operation mode of the transistor 3 and the storage mode of the RS flip-flop is thus supported. When the trigger stores the state of "logical" 0 ", when the transistor 4 is open, the processes proceed similarly.

RS-flip-flop state is set by applying to one of its inputs (R-input (1) or S-input (2)) a control signal in the form of an incoming current quantum. Let the trigger be in the logical 1 state. The supply of a current quantum to the R-input (1) leads to a "loss" of current through the transistor 3, it closes, and the input, and therefore the output current of the current mirror 6 at the auxiliary output 13 and the current quantum of the reference current source 14 through the transistor disappear 4 is fed to the input of the current mirror 7. As a result, the current quantum of the reference current source 10 is sent to the auxiliary output 15 of the current mirror 7. At the end of the control quantum of the current at the R-input (1), the established state is saved. Switching the trigger from the state “logical 0” to the state “logical 1” using the control current quantum at the S-input (2) is similar.

Shown in the drawings of Fig.6, Fig.7, Fig.10, Fig.13, Fig.15 simulation results confirm the indicated properties of the claimed circuit, which can also be implemented in the basis of CMOS transistors. It should be noted that the short-term pulses at the trigger output that occur at the time of switching the input signals, which are also characteristic of other known RS triggers, are determined by different switching times of current mirrors and can be eliminated in real circuits using technology.

Thus, the considered circuitry solutions of RS triggers are characterized by the multi-valued state of internal signals and the binary representation of the signal at its current output and can be used as the basis for computing and control devices using multi-valued linear algebra, a particular case of which is Boolean algebra.

BIBLIOGRAPHIC LIST

1. Patent US 8.115.522 fig.2

2. Patent US 7.626.433

3. Patent US 7.236.029 fig. 3

4. US Patent 6,268,752 fig. 4

5. Patent US 6.486.720

6. Patent application US 2002/0003443 fig.4

7. Patent US 6.714.060

8. Patent US 5.025.174

9. Patent US 5.945.858

10. Patent US 5.892.382 fig.2

11. US patent 5.844.437 fig.2

12. US patent 5.220.212

13. Patent US 5.815.019 fig. 1

14. Patent US 5.541.544 fig. 1

15. US patent 5.001.361 fig. 3

16. US patent 5.969.556 fig. 1

17. Patent US 4.156.819 fig.2

18. Patent US 4.779.009 fig. 4

19. Patent US 4.309.625 fig. 4

20. Patent US 3.305.728

21. Malyugin V.D. Realization of Boolean functions by arithmetic polynomials. // Automation and Telemechanics, 1982, No. 4, p. 84-93.

22. Chernov N.I. Fundamentals of the theory of the logical synthesis of digital structures over the field of real numbers. // Monograph. - Taganrog: TRTU, 2001 .-- 147 p.

23. Chernov N.I. Linear synthesis of digital structures ASOIU.// Textbook. - Taganrog: TRTU, 2004 - 118 p.

Claims (2)

1. RS-trigger with a multi-valued internal representation of signals, containing R (1) and S (2) inputs, output transistors (3) and (4), the bases of which are connected to the auxiliary voltage source (5), the first (6) and second (7) inverting amplifiers with the corresponding first (8) and second (9) current outputs, the first (10) reference current source, the first (11) and second (12) power supply buses, characterized in that as the first (6) and the second (7) inverting amplifiers use the corresponding first (6) and second (7) current mirrors, consistent with the first (11) by the power supply bus, the input of the first (6) current mirror is connected to the collector of the first (3) output transistor, the auxiliary current output (13) of the first (6) current mirror is connected to the emitter of the second (4) output transistor and S-input (2) of the trigger and also through the second (14) reference current source is connected to the second (12) bus of the power source, the input of the second (7) current mirror is connected to the collector of the second (4) output transistor, the auxiliary current output (15) of the second (7) current mirror connected to the emitter of the first (4) output transi torus and R-input (1) of the trigger, as well as through the first (10) reference current source is connected to the second (12) bus of the power source, and the current outputs (8) and (9) of the first are used as the antiphase current outputs of the RS-trigger (6) and second (7) current mirrors. 2. RS-trigger with a multi-valued internal representation of signals according to claim 1, characterized in that the first (16) and second (17) additional transistors are introduced into the circuit, the bases of which are connected to the auxiliary voltage source (5), the emitters are connected to the emitters of the corresponding the first (3) and second (4) output transistors, and the collectors are connected to the corresponding auxiliary current outputs (18) and (19) of the device.

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