RU2362266C1 - Self-synchronising single-stage d flip-flop with high active level of control signal - Google Patents

Abstract

FIELD: computer engineering.

SUBSTANCE: invention relates to pulse and computer engineering and can be used in designing self-synchronising flip flops, register and computation devices and digital signal processing systems. The technical outcome of the invention is achieved due to that, in a circuit containing a bistable cell, indicator element, data input, control input, true and complementary outputs and an indicator output, there is also OR-AND-NOT element and an inverter.

EFFECT: provision for self-synchronisation of a single-stage D flip-flop with single-phase coding of the data input, with high active level of control signal and paraphrase coding of the data output.

5 cl, 5 dwg

Description

Self-synchronous single-cycle D-flip-flop with a high active level of the control signal refers to pulse and computer technology and can be used to build self-synchronous trigger, register and computing devices, digital information processing systems.

Known D-trigger [1] containing four AND-NOT elements and an inverter.

A disadvantage of the known device is the lack of means for indicating the end of transients.

The closest to the proposed solution by technical nature and adopted as a prototype is a self-synchronous RS-trigger [2] containing a bistable cell on the elements OR-AND-NOT with paraphase coding of information inputs or outputs and an indicator element OR-AND-NOT.

The disadvantage of the prototype is that it only works with data presented in a paraphase code, which doubles the number of information links between a multi-bit source of input information and a register based on this trigger and does not allow using it as an interface element between synchronous and self-synchronous circuits.

The problem solved in the invention is to provide a self-synchronous implementation of a single-cycle D-flip-flop with a single-phase information input and a high active control signal level, which guarantees the operability of the trigger for any delays of its constituent elements.

This is achieved by the fact that in the trigger containing a bistable cell, an indicator element, an information input, a control input, direct and inverse information outputs and an indicator output, an inverter at the information input and an OR-AND-NOT element are introduced, and the bistable cell and indicator element are implemented on the elements OR-AND-NOT, the information input is connected to the inverter input, the second input of the first group of inputs OR the first element OR-AND-NOT, the first input of the first group of inputs OR the third element OR-AND-NOT and the first input of the first group inputs OR of the fourth element OR-AND-NOT, the control input is connected to the input of the second group of inputs OR of the first element OR-AND-NOT, the output of which is connected to the second inputs of the first groups of inputs OR of the second and third elements OR-AND-NOT and the third inputs of the first and the second group of inputs OR of the fourth element OR-AND-NOT, the inverter output is connected to the first inputs of the first groups of inputs OR of the first and second elements OR-AND-NOT and the first input of the second group of inputs OR of the fourth element OR-AND-NOT, the output of the second element OR-AND-NOT connected to the second input ne the first group of inputs OR of the fourth element OR-AND-NOT, the input of the second group of inputs OR of the third element OR-AND-NOT and the direct information output of the trigger, the output of the third element OR-AND-NOT connected to the second input of the second group of inputs OR of the fourth element OR- AND-NOT, by the input of the second group of inputs OR of the second element OR-AND-NOT and the inverse information output of the trigger, the output of the fourth element OR-AND-NOT is connected to the indicator output of the trigger.

The proposed device meets the criterion of "significant differences". The use of OR-AND-NOT elements and inverters to implement a D-trigger is known. However, their use in this case allowed to achieve the effect expressed by the purpose of the invention.

Since the introduced structural connections in similar technical solutions are not known, the device can be considered to have significant differences.

Figure 1 shows a diagram of a self-synchronous single-cycle D-flip-flop with a single-phase data input.

The D-trigger circuit contains an inverter 1, four elements OR-AND-NOT 2-5, information input 6, control input 7, direct information output 8, inverse information output 9 and indicator output 10, information input 6 is connected to the input of inverter 1, the second input of the first group of inputs OR element OR-AND-NOT 2, the first input of the first group of inputs OR element OR-AND-4 and the first input of the first group of inputs OR element OR-AND-NOT 5, the control input 7 is connected to the input of the second group inputs OR element OR-AND-NOT 2, the output of which is connected to the second inputs of the first groups of inputs OR elements OR-AND-NOT 3 and 4 and the third inputs of the first and second groups of inputs OR elements OR-AND-NOT 5, the inverter 1 output is connected to the first inputs of the first groups of inputs OR elements OR-AND-NOT 2 and 3 and the first input of the second group of inputs OR element OR-AND-NOT 5, the output of the element OR-AND-NOT 3 is connected to the second input of the first group of inputs OR element OR-AND-NOT 5, the input of the second group of inputs OR 4 and the direct information output of trigger 8, the output of the OR-AND-NOT 4 element is connected to the second input of the second group of inputs OR of the OR-AND-N element E 5, the input of the second group of inputs OR of the element OR-AND-NOT 3 and the inverse information output of the trigger 9, the output of the element OR-AND-NOT 5 is connected to the indicator output of the trigger 10.

The scheme works as follows. Recording a new state from the information input 6 into the bistable cell formed by elements 3 and 4 is provided by supplying an active high level to the control input 7. The output of element 2 switches to a low state, thereby opening the inputs of the bistable cell on elements 3 and 4. If the information input 6 is low, the OR-AND-NOT 3 element will switch to state "1", and the element OR-AND-NOT 4 - to state "0". In this case, the indicator output 10 goes into state "1". With a low signal level at the control input 7, the output of element 2 switches to a high state and the bistable cell is locked at the inputs, maintaining the state of its outputs. In this case, the indicator output 10 will enter the state "0". Element 5 performs the function of an indicator of the end of transients in all elements of a single-cycle D-flip-flop and a phase regulator of its switching. The value "1" at the output of element 5 indicates the end of the trigger switching to the working phase, and the value "0" indicates the end of the switching of the trigger to the spacer - the phase of storing its state, thereby ensuring self-synchronization of its functioning.

The features of this scheme in comparison with the prototype are as follows.

The trigger information input is single-phase, which allows the use of a D-trigger as an interface element between synchronous and self-synchronous circuits. The updated indicator output captures the moment of the end of transient processes in all trigger elements, both those that were part of the prototype and newly introduced, which provides an indication of all elements in the self-synchronous circuit.

Thus, the proposed device provides self-synchronous operation of a single-cycle D-flip-flop with a single-phase information input and a high active level of the control signal. The objective of the invention is achieved.

In addition, the proposed single-cycle D-trigger allows you to halve the number of information links between a multi-bit source of input information and a register based on this self-synchronous D-trigger.

This single-cycle D-flip-flop does not have the inputs of the “0” and “1” settings, which in a number of practical cases is a significant drawback. However, the proposed option is easily converted to a trigger with a preset.

Figure 2 shows a diagram of a self-synchronous single-cycle D-flip-flop with a high active level of the control signal with a zero setting input 11. The circuit differs from the circuit in figure 1 in that the second group of inputs OR of the OR-AND-NOT 3 element contains two inputs, the first of which is connected to the input of the zero setting 11, and the second to the output of the element OR-AND-NOT 4, as in the circuit in figure 1. Zero setting is performed by applying to the control input 7 low level, and at the input of the installation 11 - high level. As a result, the output of element 2 switches to the high level state, the output of the OR-AND-NOT 3 element, which forms the direct output of trigger 9, switches to the logic zero state (low level), and the OR-AND-NOT-4 element, which forms the inverse output of trigger 8 , then goes into a high level state, completing the installation.

Figure 3 shows a diagram of a self-synchronous single-cycle D-flip-flop with a high active level of the control signal with setting unit 11. The circuit differs from the circuit in figure 1 in that the second group of inputs OR of the element OR-AND-NOT 4 contains two inputs, the first of which is connected to the input of the installation unit 11, and the second to the output of the element OR-AND-NOT 3, as in the circuit in figure 1. Unit installation is carried out by applying to the control input 7 low level, and at the input of the installation 11 - high level. As a result, the output of element 2 switches to the high level state, the output of the OR-AND-NOT 4 element, which forms the inverse output of trigger 8, switches to the logical zero state (low level), and the output of the element OR-AND-NOT 3, which forms the direct trigger output 9, thereafter goes into a high level state.

Figure 4 shows a diagram of a self-synchronous single-cycle D-flip-flop with a high active level of the control signal with the setting of unity and zero. The circuit differs from the circuit in figure 2 in that the second group of inputs OR of the OR-AND-NOT 4 element contains two inputs, the first of which is connected to the unit installation input 12, and the second to the output of the OR-AND-NOT 4 element, as and in the circuit of FIG. 1. The setting of zero or one is carried out by the method described above. The simultaneous supply to the inputs of the installation of zero 11 and unit 12 low level is prohibited.

Figure 5 shows a diagram of a self-synchronous single-cycle D-flip-flop with a high active level of the control signal with a single-phase data input and phase output 11 connected to the output of the element OR-AND-NOT 2. Phase (initiating the phase of the D-trigger) output serves to accelerate triggering of the device-source of the information signal: permission for its transition to the opposite phase of operation is issued as soon as the OR-AND-NOT 2 element in the trigger switches after a new value arrives at control input 7, without waiting for the end Switchgears the other elements in the trigger circuit. A similar output can be used in all other versions of the D-trigger described above.

Information sources

1. Shilo V.L. Popular Digital Chips: A Guide. 2nd ed., Rev. - Chelyabinsk: Metallurgy, Chelyabinsk Department., 1989. - Fig. 1.50a.

2. Astakhanovsky A.G., Varshavsky V.I., Marakhovsky V.B. and other aperiodic automata. // Ed. V.I. Warsaw. - M .: Nauka, 1976 .-- Fig. 2.7a.

Claims (5)

1. Self-synchronous single-cycle D-flip-flop with a high active level of the control signal, containing a bistable cell and indicator element, information input, control input, direct and inverse information outputs and indicator output, characterized in that the inverter at the information input and the OR element are introduced into the circuit -AND, and the bistable cell and indicator element are implemented on the OR-AND-NOT elements, the information input is connected to the inverter input, the second input of the first group of inputs OR the first AND-OR-NOT element, the first input the first group of inputs OR the third element OR-AND-NOT and the first input of the first group of inputs OR the fourth element AND-OR-NOT, the control input is connected to the input of the second group of inputs OR the first element AND-OR-NOT, the output of which is connected to the second inputs of the first groups of inputs OR of the second and third elements AND-OR-NOT and the third inputs of the first and second groups of inputs OR of the fourth element OR-AND-NOT, the inverter output is connected to the first inputs of the first groups of inputs OR of the first and second elements OR-AND-NOT and the first the input of the second group of inputs OR fourth about the AND-OR-NOT element, the output of the second OR-AND-NOT element is connected to the second input of the first group of inputs OR of the fourth AND-OR-NOT element, the input of the second group of inputs OR of the third OR-AND-NOT element and the direct trigger information output, the output of the third element OR-AND-NOT is connected to the second input of the second group of inputs OR of the fourth element AND-OR-NOT, the input of the second group of inputs OR of the second element OR-AND-NOT and the inverse information output of the trigger, the output of the fourth element OR-AND-NOT connected to the indicator output of the trigger. 2. Self-synchronous single-cycle D-flip-flop with a high active level of the control signal according to claim 1, characterized in that a zero-setting input is entered into it, and the second group of inputs OR of the second element OR-AND-NOT has two inputs, the first of which is connected to the input is set to zero, and the second input is connected to the output of the third element OR-AND-NOT. 3. The self-synchronous single-cycle D-flip-flop with a high active level of the control signal according to claim 1, characterized in that the unit setting input is entered into it, and the second group of inputs OR of the third element OR-AND-NOT has two inputs, the first of which is connected to the unit installation input, and the second input is connected to the output of the second element OR-AND-NOT. 4. A self-synchronous single-cycle D-flip-flop with a high active level of the control signal according to claim 2, characterized in that the unit setting input is entered into it, and the second group of inputs OR of the third element OR-AND-NOT has two inputs, the first of which is connected to the unit installation input, and the second input is connected to the output of the second element OR-AND-NOT. 5. Self-synchronous single-cycle D-flip-flop with a high active level of the control signal according to any one of claims 1 to 4, characterized in that a phase output connected to the output of the first element OR-AND-NOT is introduced into the circuit.

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