RU2693320C1 - Self-synchronizing dynamic single-cycle d-flip-flop with zero spacer - Google Patents

Abstract

FIELD: computer equipment.

SUBSTANCE: invention relates to pulse and computer equipment and can be used in construction of self-synchronizing trigger, register and computing devices, digital information processing systems. Combined indicator output in self-synchronous single-cycle D-flip-flop with zero spacer is converted into serial indicator output (output with memory). This conversion is realized by introducing an additional element NOT between the combination part of the indicator element and its external output and introduction of two additional links. First connection provides connection of a combination indicator output to additional trigger inputs (bistable cell). Second link provides connection of the additional element NOT to additional inputs of the indicator element, which transfers it from the combination class to the serial class.

EFFECT: technical result consists in acceleration of interaction of D-flip-flop with source of its information input due to reduction of time, during which state of information input of D-flip-flop should not change after appearance of high level at its control input.

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Description

The self-synchronous dynamic single-cycle D-trigger with zero spacer refers to the pulse and computing technology and can be used in the construction of self-synchronous trigger, register and computing devices, digital information processing systems.

Known dynamic asynchronous D-flip-flop [1], which contains six AND-NOT elements and provides for recording information into the trigger and blocking the information input after the active edge of the clock input arrives.

A disadvantage of the known device is the lack of means for indicating the end of transients in the elements of a trigger.

Closest to the proposed solution to the technical nature and adopted as a prototype is a self-timed single-ended D-trigger with a high active level of the control signal [2], hereinafter referred to as a D-trigger, containing one inverter and four elements OR-AND-NOT. The trigger provides for recording the status of the information input and switching to the working phase by the high level of the control input, blocking the information input and switching to the spacer phase by the low level of the control input and controlling the end of transients when switching to the spacer and working phases.

The disadvantage of the prototype is a long period of time after the appearance of a high level at the D-flip-flop control input, corresponding to a high-level duration at the control input, during which the state of the information input should not change to avoid disrupting the self-timed signal generation discipline and interaction of self-timed devices.

The problem solved by the claimed invention is to accelerate the interaction of the D-trigger with the source of its information input by reducing the time during which the state of the information input of the D-trigger does not change after the appearance of a high level at its control input. Such an acceleration of D-flip-flop interaction with the source of its information input meets the requirements of synchronous interfaces and provides the possibility of using the proposed self-synchronous D-flip-flop in a synchronous environment.

This is achieved by the fact that the combination indicator output in the self-synchronous single-ended D-trigger with zero spacer (prototype) is converted into a sequential indicator output (memory output). This transformation is implemented by the introduction of an additional element NOT between the combining part of the indicator element and its external output and the introduction of two additional connections. The first connection provides the connection of a combination indicator output to additional trigger inputs (a bistable cell), which guarantees the trigger immunity to changes in the state of the information input components. The second connection provides the connection of an additional element NOT to the additional inputs of the indicator element, which transfers it from the combining class to the sequential class and ensures the immunity of the indicator output to a change in the state of the information input components.

- The use of feedback in asynchronous triggers is known, for example, in a T-trigger [3]. However, using them in a self-timed D-trigger, taking into account the specifics of the operation of self-timed devices, allowed to achieve the effect expressed by the aim of the invention. The essential difference between the proposed implementation of feedbacks from similar solutions in asynchronous circuitry lies in the fact that in this case feedbacks are used to prevent unwanted switching of the trigger, and not to prepare it for switching to the opposite state. This allows you to speed up the blocking of the information input of the trigger after the active level of the control signal enables the recording of the state of the information input to the trigger, and ensure its self-synchronization when using an additional inverter, as described below.

Since the introduced constructive links in similar technical solutions are not known (it was not previously known from information sources published in the world), the device can be considered as meeting the criteria of novelty. In the prior art, only objects are known that have features that ensure the trigger's immunity to a change in the state of the information input components and are described in the formula. The objects that ensure the immunity of the indicator of the end of transients to a change in the state of the components of the information input and described in the formula are not known, which meets the criteria of novelty of the invention. The text of the application describes all the tools and methods necessary to implement the solution, as it is presented in the claims, which meets the criterion of industrial applicability. FIG. 1 shows a diagram of a self-synchronous dynamic single-ended D-flip-flop with zero spacer.

The scheme contains the first 1 and second 2 inverters and four elements OR-AND-NO 3-6, single-phase information input 7, control input 8, information bi-phase output 9-10, control signal output 11 and indicator output 12, with single-phase information input 7 connected to the input of the first inverter 1, to the second input of the first group of inputs OR the first element OR-AND-NOT 3, the first input of the first group of inputs OR the third element OR-AND-NOT 5 and to the first input of the first group of inputs OR the fourth element OR-AND -NOT 6, control input 8 trigger is connected to the entrance to OPA group of inputs OR of the first element OR-AND-NOT 3, the output of the first inverter 1 is connected to the first inputs of the first groups of inputs OR the first 3 and second 4 elements OR-AND-NOT and to the first input of the second group of inputs OR the fourth element OR-AND- NOT 6, the output of the first element OR-AND-NO 3 is connected to the second inputs of the first groups of inputs OR the second 4 and third 5 elements OR-AND-NOT, to the third inputs of the first and second groups of inputs OR and the first input of the third group of inputs OR the fourth element OR-AND-NOT 6 and the output of the control signal 11 trigger, the output of the second el ment OR-AND-NOT 4 is connected to the input of the second group of inputs OR the third element OR-AND-NOT 5, the second input of the first group of inputs OR the fourth element OR-AND-NOT 6 and the direct component of the bi-phase information output 9 of the trigger, the output of the third element OR -AND-NOT 5 is connected to the input of the second group of inputs OR the second element OR-AND-NOT 4, the second input of the second group of inputs OR the fourth element OR-AND-NOT 6 and the inverse component of the bi-phase information output 10 trigger, the third inputs of the first groups of inputs OR second 4 and third 5 elements OR-AND-NOT connected to the output of the fourth element OR-AND-NOT 6 and the input of the second inverter 2, the second input of the third group of inputs OR the fourth element OR-AND-NOT 6 is connected to the output of the second inverter 2 and to the indicator output 12 of the trigger.

The scheme works as follows. The recording of the state of the single-phase information input 7 into the trigger occurs when a high (operating) level arrives at the control input of the 8 D-flip-flop. The end of the recording (completion of switching of all elements of the trigger scheme initiated in the process of writing) to the bistable memory cell on the OR-AND-NE 4 and 5 elements is fixed by the indicator element on the OR-AND-NOT 6 element, confirming the output information state bi-phase output 9 - 10 of the trigger state of the information input 7. The output of the indicator element 6 switches to the state of the logical unit, which ensures the recording of a single-phase information input 7 trigger in the cell pa The cells on elements 4 and 5. At the same time, the inverter 2 switches to the logical zero state, prohibiting the switching of the indicator element 6 due to the possible switching of the trigger information input 7 to the state not corresponding to the memory cell state on the elements 4 and 5. The output of the inverter 2 forms the indicator output 12, notifying devices connected to this D-flip-flop about the completion of writing to the trigger and allowing the source of information input 7 of the trigger to no longer maintain the current state of information input 7. Source to the information input of this D-flip-flop, having received this notification, initiates the switching of the control signal of the 8 flip-flop to the inactive (spacer) state of the logical zero and at the same time, without waiting for a response from the D-flip-flop, can start generating a new value of the information input 7. D- the trigger accepts the state of logical zero (spacer) of control input 8, transfers the output of the control signal to the state of logical unit and initiates the switching of the indicator element 6 to the state of logical zero, removing the block Recording information entry 7 into the memory cell on elements 4 and 5 as an indicator element (the blocking itself remains, but is already implemented by the control input) and prohibiting a change in the state of indicator element 6 due to incompatibility of the information input 7 state with the memory cell on elements 4 and 5. After the inverter 2 switches to the logical unit state, the D-flip-flop is ready to record the new value of information input 7, about which it notifies the source of information input 7 with a high level of indicator output 1 2

Features of this scheme compared to the prototype are as follows.

A trigger has feedbacks that ensure that the information input of the trigger is blocked after recording its state in the trigger memory cell and blocking the indicator element until a low level appears at the trigger control input. This allows the trigger information input source to start generating a new information entry value, without waiting for switching to the spacer (low level) of the trigger control input, which in the prototype is a prerequisite for adhering to the self-timed signal generation discipline in the self-timed circuit.

Thus, the proposed device accelerates the interaction of the D-flip-flop with the source of its information input and provides the possibility of using the proposed self-timed D-flip-flop in a synchronous environment. This ensures the receipt of the stated result.

In practice, the D-trigger often requires presetting to a certain state before starting (after power on) or during circuit operation.

As examples, we will show the implementation of a self-synchronous dynamic single-ended D-flip-flop with a zero spacer with asynchronous reset and set-up.

FIG. Figure 2 shows the implementation of a self-synchronous dynamic single-ended D-trigger with zero spacer with asynchronous reset. This implementation is different from the implementation in FIG. 1 by the fact that a second input is connected to the second group of inputs OR of the second element OR-AND-NO 4, which is connected to the input of the asynchronous reset 13.

The trigger is reset to a state with a low level on the direct component of the bi-phase output 9 and a high level on the inverse component of the bi-phase output 10 when the spacer state of the control input 8 of the trigger occurs and occurs as follows. With a low signal level at the control input 8, the output of the OR-AND-NOT 3 element by its high level blocks the recording of information input 7 to the bistable cell on elements 4 and 5 and maintains the output of the indicator element OR-AND-6 6 in the state of logical zero. The supply at this time of a high level to the input of the asynchronous reset 13 leads to switching the output of the element OR-AND-NOT 4 and, accordingly, the direct component of the bi-phase output 9, to a state of logical zero, which, in turn, causes the switching of the element OR-AND- NOT 5 and the inverse component of the bi-phase output 10 in the state of a logical unit. Trigger reset complete.

FIG. 3 shows the implementation of a self-synchronous dynamic single-ended D-trigger with zero spacer with asynchronous installation. This implementation is different from the implementation in FIG. 1 by the fact that a second input is connected to the second group of inputs OR of the third element OR-AND-NOT 5, which is connected to the input of the asynchronous installation 14.

Setting the trigger to a state with a high level on the direct component of the bi-phase output 9 and a low level on the inverse component of the bi-phase output 10 is carried out with the spacer state of the control input 8 of the trigger and proceeds as follows. With a low signal level at the control input 8, the output of the OR-AND-NOT 3 element by its high level blocks the recording of information input 7 to the bistable cell on elements 4 and 5 and maintains the output of the indicator element OR-AND-6 6 in the state of logical zero. The supply at this time of a high level to the input of the asynchronous installation 14 leads to switching the output of the element OR-AND-NOT 5 and, accordingly, the inverse component of the biphasic output 10 to the state of logical zero, which, in turn, causes the switching of the element OR-AND-NOT 4 and the direct component of the bi-phase output 9 in the state of a logical unit. Trigger installation is complete.

FIG. 4 shows a scheme for implementing a self-synchronous dynamic single-ended D flip-flop with zero spacer with asynchronous reset and set-up. This scheme is different from the scheme in FIG. 1 by the fact that a second input is connected to the second groups of OR inputs of the second 4 and third 5 OR-AND-NOT elements, connected to the inputs of asynchronous reset 13 and asynchronous installation 14, respectively. The reset and installation of the D-flip-flop is performed with the spacer state of the control input 8 in accordance with the reset procedures described above and the installation of the trigger options shown in FIG. 2 and 3.

Sources:

[1] Tietze U., Schenk K. Semiconductor Circuit Engineering: A Reference Manual. Per. with him. M: Mir, 1982. - 512 s, fig. 9.34.

[2] Sokolov, IA, Stepchenkov, Yu.A., Dyachenko, Yu.G., Zakharov, V.N. Self-synchronous single-ended D-trigger with a high active level of the control signal: Pat. No. 2362266. Registered on 07/20/09. Publ. in BI, 2009, №20. - 7 s.

[3] Ugryumov E.P. Digital circuit design. - SPb .: BHV - St. Petersburg, 2000. 528 p. ISBN 5-8206-0100-9, fig. 3.7 (b).

Claims (1)

Self-synchronous dynamic single-ended D-trigger with zero spacer containing one inverter and four elements OR-AND-NOT, control input, single-phase information input, direct and inverse components of the bi-phase information output, control signal output and indicator output, with a single-phase information input connected to the input of the inverter, the second input of the first group of inputs OR the first element OR-AND-NOT, the first input of the first group of inputs OR the third element OR-AND-NOT and the first input of the first group of inputs OR the fourth element enta OR-AND-NOT, the trigger control input is connected to the input of the second group of inputs OR of the first element OR-AND-NOT, the output of the inverter is connected to the first inputs of the first groups of inputs OR of the first and second elements OR-AND-NOT and to the first input of the second group the inputs of the fourth element OR-AND-NOT, the output of the first element OR-AND-NOT is connected to the second inputs of the first groups of inputs OR the second and third elements OR-AND-NOT, to the third inputs of the first and second groups of inputs OR the fourth element OR-AND -NOT and trigger control signal output, second element output nta OR-AND-NOT connected to the input of the second group of inputs OR the third element OR-AND-NOT, the second input of the first group of inputs OR the fourth element OR-AND-NOT and the direct component of the bi-phase information output of the trigger, the output of the third element OR-AND-NOT connected to the input of the second group of inputs OR the second element OR-AND-NOT, the second input of the second group of inputs OR the fourth element OR-AND-NOT and the inverse component of the bi-phase information output of the trigger, characterized in that it introduces the second inverter, the third inputs into the first login groups OR of the second and third elements OR-AND-NOT and the third group of inputs OR to the fourth element OR-AND-NOT, with the third inputs of the first groups of inputs OR the second and third elements OR-AND-NOT connected to the output of the fourth element OR-AND-NOT and the input of the second inverter, the first and second inputs of the third group of inputs OR the fourth element OR-AND-NOT are connected to the outputs of the first element OR-AND-NOT and the second inverter, respectively, the output of the second inverter is connected to the indicator output of the trigger.

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