RU2693318C1 - Self-synchronizing dynamic single-cycle d-flip-flop with single spacer - Google Patents

Abstract

FIELD: computer equipment.

SUBSTANCE: invention relates to pulse and computer technology. Combined indicator output in self-synchronous single-cycle D-flip-flop with single spacer is converted into a serial indicator output (output with memory). This conversion is realized by introducing an additional element NOT between the combination part of the indicator element and its external output and introduction of two additional links. First connection provides connection of a combination indicator output to additional trigger inputs (bistable cell), which guarantees immunity of the flip-flop to change of state of information input components. Second link provides connection of the additional element NOT to additional inputs of the indicator element, which switches it from the combinational class to the sequential class and guarantees non-susceptibility of the indicator output to change of state of components of the information input.

EFFECT: technical result consists in acceleration of interaction of D-flip-flop with source of its information input due to reduction of time, during which state of information input of D-flip-flop should not change after occurrence of low level at its control input.

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Description

The self-synchronous dynamic single-cycle D-trigger with a single spacer refers to the pulse and computing technology and can be used in the construction of self-synchronous trigger, register and computing devices, digital information processing systems.

Known dynamic asynchronous D-flip-flop [1], which contains six AND-NOT elements and provides for recording information into the trigger and blocking the information input after the active edge of the clock input arrives.

A disadvantage of the known device is the lack of means for indicating the end of transients in the elements of a trigger.

The closest to the proposed solution to the technical essence and therefore adopted as a prototype is a self-timed single-ended D-trigger with a low active level of the control signal [2], hereinafter referred to as a D-trigger, containing one inverter and four AND-OR-HE elements. The trigger provides for recording the state of the information input and switching to the working phase by a low level control input, blocking the information input and switching to the spacer phase by a high level control input and controlling the end of transients when switching to the spacer and working phases.

The disadvantage of the prototype is a long period of time after the low level appears at the D-flip-flop control input, corresponding to the low-level duration at the control input, during which the state of the information input should not change to avoid disrupting the self-synchronous signal generation discipline and the interaction of self-timed devices.

The problem solved by the present invention is to reduce the time during which the state of the information input of the D-flip-flop should not change after the appearance of a low level at its control input. Such an acceleration of D-flip-flop interaction with the source of its information input meets the requirements of synchronous interfaces and provides the possibility of using the proposed self-synchronous D-flip-flop in a synchronous environment.

This is achieved by the fact that the combination indicator output in the self-synchronous single-ended D-trigger with a single spacer (prototype) is converted into a sequential indicator output (memory output). This transformation is implemented by the introduction of an additional element NOT between the combining part of the indicator element and its external output and the introduction of two additional connections. The first connection provides the connection of a combination indicator output to additional trigger inputs (a bistable cell), which guarantees the trigger immunity to changes in the state of the information input components. The second connection provides the connection of an additional element NOT to the additional inputs of the indicator element, which transfers it from the combining class to the sequential class and ensures the immunity of the indicator output to a change in the state of the information input components.

The use of feedback in asynchronous triggers is known, for example, in a T-trigger [3]. However, using them in a self-timed D-trigger, taking into account the specifics of the operation of self-timed devices, allowed to achieve the effect expressed by the aim of the invention. The essential difference between the proposed implementation of feedbacks from similar solutions in asynchronous circuitry lies in the fact that in this case feedbacks are used to prevent unwanted switching of the trigger, and not to prepare it for switching to the opposite state. This allows you to speed up the blocking of the information input of the trigger after the active level of the control signal enables the recording of the state of the information input to the trigger, and ensure its self-synchronization when using an additional inverter, as described below.

Since the introduced constructive links in similar technical solutions are not known (it was not previously known from information sources published in the world), the device can be considered as meeting the criteria of novelty. In the prior art, only objects are known that have features that ensure the trigger's immunity to a change in the state of the information input components and are described in the formula. The objects that ensure the immunity of the indicator of the end of transients to a change in the state of the components of the information input and described in the formula are not known, which meets the criteria of novelty of the invention. The text of the application describes all the tools and methods necessary to implement the solution, as it is presented in the claims, which meets the criterion of industrial applicability.

FIG. 1 shows a diagram of a self-synchronous dynamic single-ended D-flip-flop with a single spacer.

The scheme contains the first 1 and second 2 inverters and four elements AND-OR-NOT 3-6, single-phase information input 7, control input 8, information bi-phase output 9-10, control signal output 11 and indicator output 12, with single-phase information input 7 connected to the input of the first inverter 1, to the second input of the first group of inputs AND the first element AND-OR-NOT 3, the first input of the first group of inputs AND the third element AND-OR-NOT 5 and to the first input of the first group of inputs AND the fourth element AND-OR -NOT 6, control input 8 trigger connected to the input of the second c ppy inputs And the first element AND-OR-NOT 3, the output of the first inverter 1 is connected to the first inputs of the first groups of inputs AND the first 3 and second 4 elements AND-OR-NOT and the first input of the second group of inputs AND the fourth element AND-OR-NOT 6, the output of the first element AND-OR-NO 3 is connected to the second inputs of the first groups of inputs AND the second 4 and the third 5 elements AND-OR-NOT, to the third inputs of the first and second groups of inputs AND and the first input of the third group of inputs AND the fourth element AND -OR-NOT 6 and control signal output 11 trigger, the output of the second element AND-OR-NOT 4 podkl yuchen to the input of the second group of inputs AND the third element AND-OR-NOT 5, the second input of the first group of inputs AND the fourth element AND-OR-NOT 6 and the direct component of the bi-phase information output 9 of the trigger, the output of the third element AND-OR-NOT 5 is connected to the input of the second group of inputs AND the second element AND-OR-NOT 4, the second input of the second group of inputs AND the fourth element AND-OR-NOT 6 and the inverse component of the bi-phase information output 10 of the trigger, the third inputs of the first groups of inputs AND the second 4 and the third 5 elements AND -Or-NOT connected to the fourth outlet element AND-OR-NOT 6 and the input of the second inverter 2, the second input of the third group of inputs AND the fourth element AND-OR-NOT 6 is connected to the output of the second inverter 2 and to the indicator output 12 of the trigger.

The scheme works as follows. The recording of the state of the single-phase information input 7 into the trigger occurs when a low (operating) level is received at the control input of the 8 D-flip-flop. The end of the recording (completion of switching of all elements of the trigger scheme initiated in the process of writing) to the bistable memory cell on the AND-OR-NOT 4 and 5 elements is fixed by an indicator element on the AND-OR-NOT 6 element, confirming with a low level on its output that the information state corresponds bi-phase output 9-10 of the trigger state of the information input 7. The output of the indicator element 6 is switched to the state of logical zero, which ensures that the recording of the single-phase information input 7 of the trigger in the memory cell is blocked on elements 4 and 5. At the same time, inverter 2 switches to the state of logical unit, prohibiting switching of indicator element 6 due to possible switching of information input 7 of the trigger to a state not corresponding to the state of the memory cell on elements 4 and 5. The output of inverter 2 forms indicator output 12 that notifies devices connected to this D-trigger to complete recording into the trigger and allows the source of information input 7 of the trigger to no longer maintain the current state of information input 7. Source information input D-flip-flop, receiving this notification, initiates the switching of the control signal 8 flip-flop to the inactive (spacer) state of the logical unit and at the same time, without waiting for a response from the D-flip-flop, can start generating a new value of the information input 7. D-flip-flop the state of the logical unit (spacer) of the control input 8, translates the output of the control signal to the state of logical zero and initiates the switching of the indicator element 6 to the state of the logical unit, releasing the lock recording information input 7 into the memory cell on elements 4 and 5 as an indicator element (the blocking itself remains, but is already implemented by the control input) and prohibiting a change in the state of indicator element 6 due to the discrepancy between the state of information input 7 and the memory cell on elements 4 and 5. After when the inverter 2 switches to the logical zero state, the D flip-flop is ready to record the new value of information input 7, about which it notifies the source of information input 7 with a low level indicator output 12.

Features of this scheme compared to the prototype are as follows.

A trigger has feedbacks that ensure that the information input of the trigger is blocked after its status is recorded in the trigger memory cell and the indicator element is blocked until a high level appears at the trigger control input. This allows the trigger information input source to start generating a new information entry value, without waiting for switching to the spacer (low level) of the trigger control input, which in the prototype is a prerequisite for adhering to the self-timed signal generation discipline in the self-timed circuit.

Thus, the proposed device accelerates the interaction of the D-flip-flop with the source of its information input. The purpose of the invention has been achieved.

In practice, the D-trigger often requires presetting to a certain state before starting (after power on) or during circuit operation.

As examples, we will show the implementation of a self-synchronous dynamic single-ended D-flip-flop with a single spacer with asynchronous reset and set-up.

FIG. Figure 2 shows the implementation of a self-synchronous dynamic single-ended D-trigger with a single spacer with asynchronous installation. The implementation is different from the implementation in FIG. 1 by the fact that a second input is connected to the second group of inputs AND of the second element AND-OR-NO 4, which is connected to the input of the asynchronous installation 13.

Setting the trigger to a state with a high level on the direct component of the bi-phase output 9 and a low level on the inverse component of the bi-phase output 10 is carried out with the spacer state of the control input 8 of the trigger and proceeds as follows. With a high signal level at the control input 8, the output of the AND-OR-NOT 3 element by its low level blocks the recording of information input 7 to the bistable cell on elements 4 and 5 and maintains the output of the indicator element AND-OR-NOT 6 in the state of logical zero. Submission at this time of a low level to the input of the asynchronous installation 13 leads to switching the output of the AND-OR-NOT 4 element and, accordingly, the direct component of the bi-phase output 9 to the state of a logical unit, which, in turn, causes the switching of the AND-OR-NOT element 5 and the inverse component of the bi-phase output 10 to the state of logical zero. Trigger installation is complete.

FIG. Figure 3 shows the implementation of a self-timed, single-ended, single-spacer D-flip-flop with asynchronous reset. The implementation is different from the implementation in FIG. 1 in that the second input, connected to the asynchronous reset input 14, is entered in the second group of AND inputs of the third AND-OR-NOT element 5.

The trigger is reset to a state with a low level on the direct component of the bi-phase output 9 and a high level on the inverse component of the bi-phase output 10 when the spacer state (logical unit) of the control input 8 of the trigger occurs and occurs as follows. With a high signal level at the control input 8, the output of the AND-OR-NOT 3 element by its low level blocks the recording of information input 7 to the bistable cell on elements 4 and 5 and maintains the output of the indicator element AND-OR-NOT 6 in the state of logical unit. Submission at this time of a low level to the input of the asynchronous reset 14 leads to switching the output of the AND-OR-NOT 5 element and, accordingly, the inverse component of the bi-phase output 10, to the state of the logical unit, which, in turn, causes the AND-OR element to switch NOT 4 and the direct component of the bi-phase output 9 to the state of logical zero. Trigger reset complete.

FIG. Figure 4 shows the implementation of a self-timed, single-ended, single-spacer D-flip-flop with asynchronous reset and set-up. The implementation is different from the implementation in FIG. 1 by the fact that a second input is connected to the second groups of AND inputs of the second 4 and third 5 AND-OR-NOT elements connected to the inputs of the asynchronous installation 13 and asynchronous reset 14, respectively. The reset and installation of the D-flip-flop is performed with the spacer state of the control input 8 in accordance with the reset procedures described above and the installation of the trigger options shown in FIG. 2 and 3.

Sources:

[1] Tietze U., Schenk K. Semiconductor Circuit Engineering: A Reference Manual. Per. with him. M: Mir, 1982. - 512 p., Fig. 9.34.

[2] Stepchenkov Yu.A., Dyachenko Yu.G., Rozhdestvensky Yu.V., Filin AV Self-synchronous single-ended D-trigger with a low active level of the control signal: Pat. No. 2362267. Registered on 07/20/09. Publ. in BI, 2009, №20. - 9 s.

[3] Ugryumov E.P. Digital circuit design. - SPb .: BHV - St. Petersburg, 2000. 528 p. ISBN 5-8206-0100-9, fig. 3.7 (b).

Claims (1)

Self-synchronous dynamic single-ended D-trigger with a single spacer containing one inverter and four AND-OR-NOT elements, control input, single-phase information input, direct and inverse components of the bi-phase information output, control signal output and indicator output, with a single-phase information input connected to the input of the inverter, the second input of the first group of inputs AND the first element AND-OR-NOT, the first input of the first group of inputs AND the third element AND-OR-NOT and the first input of the first group of inputs AND the fourth element AND-OR-NOT, the trigger control input is connected to the input of the second group of inputs AND the first element AND-OR-NOT, the output of the inverter is connected to the first inputs of the first groups of inputs AND the first and second elements AND-OR-NOT and to the first input of the second group of inputs And the fourth element AND-OR-NOT, the output of the first element AND-OR-NOT is connected to the second inputs of the first groups of inputs AND the second and third elements AND-OR-NOT, to the third inputs of the first and second groups of inputs AND the fourth element AND-OR- NOT and trigger control signal output, the output of the second element AND-OR-NOT under It is connected to the input of the second group of inputs AND the third element AND-OR-NOT, the second input of the first group of inputs AND the fourth element AND-OR-NOT and the direct component of the bi-phase information output of the trigger, the output of the third element AND-OR-NOT connected to the input of the second group of inputs And the second element AND-OR-NOT, the second input of the second group of inputs AND the fourth element AND-OR-NOT and the inverse component of the bi-phase information output of the trigger, characterized in that it introduced the second inverter, the third inputs in the first groups of inputs And the second and third email AND-OR-NOT elements and the third group of inputs AND to the fourth element AND-OR-NOT, the third inputs of the first groups of inputs AND the second and third elements AND-OR-NOT connected to the output of the fourth element AND-OR-NOT and the input of the second inverter , the first and second inputs of the third group of inputs AND the fourth element AND-OR-NOT are connected to the outputs of the first element AND-OR-NOT and the second inverter, respectively, the output of the second inverter is connected to the indicator output of the trigger.

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