RU2361359C1 - Self-synchronising d-flip-flop - Google Patents

Abstract

FIELD: information technologies.

SUBSTANCE: invention relates to pulse and computer engineering and can be used in composing self-synchronising trigger, register and computing devices and systems of digital information processing. To this effect invert circuits are installed at data and driving inputs of scheme containing two step-type flip-flops; also flip-flop transient closing display device is realised on three AND-OR inverters, NOT-OR circuit and invert circuit.

EFFECT: ensuring self-synchronising of D-flip-flop with data input single-phase encoding and data output paraphrase encoding.

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Description

Self-synchronous D-flip-flop refers to pulsed and computational technology and can be used to build self-synchronous trigger, register and computing devices, digital information processing systems.

Known D-trigger [1], containing six elements AND NOT.

A disadvantage of the known device is the lack of means for indicating the end of transients.

Closest to the proposed solution by technical nature and adopted as a prototype is a D-trigger [2], containing two single-cycle triggers with paraphase coding of information inputs and outputs.

The disadvantage of the prototype is to work only with the data presented in the paraphase code, which does not allow using it as an interface element between synchronous and self-synchronous circuits

The problem solved by the invention is to provide a self-synchronous implementation of a D-flip-flop with a single-phase data input and a paraphase output without a spacer, storing its state until the next operation of writing a new state to it.

This is achieved by the fact that in the D-flip-flop, which contains two single-cycle flip-flops, an information input, a control input, a zeroing input, a direct and inverse information outputs and an indicator output, inverters at the inputs: information and control are introduced, as well as a device for indicating the end of transients in a trigger implemented on three AND-OR-NOT elements, an OR-NOT element and an inverter, the first one-stroke trigger is implemented on two AND-OR-NOT elements, and the second one-stroke trigger is implemented on two OR-AND-NOT elements, inform The input is connected to the input of the first inverter, the third input of the first group of inputs AND the second AND-OR-NOT element, the first input of the OR-NOT element and the second input of the third group of inputs AND the fourth AND-OR-NOT element, the control input is connected to the input of the second inverter and the second input of the OR-NOT element, the zeroing input is connected to the second input of the second group of inputs AND the second AND-OR-NOT element, the output of the first inverter is connected to the first input of the first group of inputs AND the first AND-OR-NOT element and the first input of the second group of inputs And fourth e element AND-OR-NOT, the output of the second inverter is connected to the second inputs of the first groups AND of the first and second elements AND-OR-NOT, the second inputs of the first groups OR of the first and second elements OR-AND-NOT, the input of the third group of inputs AND the third element AND -OR-NOT, the third input of the third group of inputs AND the fourth element AND-OR-NOT and the second input of the fourth group of inputs AND the fourth element AND-OR-NOT, the output of the element OR-NOT connected to the first input of the first group of inputs AND and the third input of the second groups of inputs AND of the fourth element AND-OR-NOT, the output of the first element This AND-OR-NOT connection is connected to the first input of the first group of inputs OR of the first element OR-AND-NOT, the first input of the second group of inputs AND the second element AND-OR-NOT, the first input of the first group of inputs AND the third element AND-OR-NOT and the first input of the third group of inputs AND the fourth element AND-OR-NOT, the output of the second element AND-OR-NOT connected to the input of the second group of inputs AND the first element AND-OR-NOT, the first input of the first group of inputs OR the second element OR-AND-NOT , the second input of the second group of inputs AND of the third element AND-OR-NOT and the second input of the second group in odes AND of the fourth AND-AND-NOT element, the output of the first OR-AND-NOT element is connected to the inverse information output of the trigger, the input of the second group of inputs OR the second element OR-AND-NOT, and the second input of the first group of inputs AND the third element AND-OR NOT, the output of the second element OR-AND-NOT connected to the direct information output of the trigger, the input of the second group of inputs OR of the first element OR-AND-NOT and the first input of the second group of inputs AND the third element AND-OR-NOT, the output of the third element AND-OR - NOT connected to the first inputs of the first and second groups of inputs AND of the fifth AND-OR-NOT element, the output of the fourth AND-OR-NOT element is connected to the second inputs of the first and third groups of inputs And the fifth element AND-OR-NOT, the third input of the first group of inputs AND the first AND-OR-NOT element and the first input of the first group of AND inputs of the second AND-OR-NOT element, the output of the fifth AND-OR-NOT element is connected to the input of the third inverter, the second input of the first group of inputs AND and the first input of the fourth group of inputs AND the fourth element AND-OR-NOT, the output of the third inverter connected to the indicator output and the second and first inputs of the second and the third group of inputs AND the fifth element AND-OR-NOT, respectively.

The proposed device meets the criterion of "significant differences". The use of AND-OR-NOT, OR-AND-NOT, OR-NOT and inverters to implement a D-trigger is known. However, their use in this case allowed to achieve the effect expressed by the purpose of the invention.

Since the introduced structural connections in similar technical solutions are not known, the device can be considered to have significant differences.

The drawing shows a diagram of a self-synchronous D-trigger.

The D-flip-flop circuit contains three inverters 1-3, an OR-NOT 4 element, five AND-OR-NOT elements 5-9, two OR-AND-NOT elements 10-11, an information input 12, a reset input 13, a control input 14 , direct information output 15, inverse information output 16 and indicator output 17, information input 12 is connected to the inverter 1 input, the third input of the first group of inputs AND element 6, the first input of element 4 and the second input of the third group of inputs AND element 8, zeroing input 13 connected to the second input of the second group of inputs of element 6, the control input 14 is connected to the inverter 2 and the second input of element 4, the output of the inverter 1 is connected to the first input of the first group of inputs And element 5 and the first input of the second group of inputs And element 8, the output of inverter 2 is connected to the second inputs of the first groups And elements 5 and 6, the second inputs of the first groups of OR elements 10 and 11, the input of the third group of inputs AND element 7, the third input of the third group of inputs AND element 8 and the second input of the fourth group of inputs AND element 8, the output of element 4 is connected to the first input of the first group of inputs AND and the third input of the second group of inputs And eleme nta 8, the output of element 5 is connected to the first input of the first group of inputs OR of element 10, the first input of the second group of inputs AND element 6, the first input of the first group of inputs AND element 7 and the first input of the third group of inputs AND element 8, the output of element 6 is connected to the input the second group of inputs AND element 5, the first input of the first group of inputs OR element 11, the second input of the second group of inputs AND element 7 and the second input of the second group of inputs AND element 8, the output of element 10 is connected to the inverse information output of trigger 16, the input of the second group to Odes OR element 11 and the second input of the first group of inputs AND element 7, the output of element 11 is connected to the direct information output of the trigger 15, the input of the second group of inputs OR element 10 and the first input of the second group of inputs AND element 7, the output of element 7 is connected to the first inputs of the first and the second group of inputs AND element 9, the output of element 8 is connected to the second inputs of the first and third groups of inputs AND element 9, the third input of the first group of inputs AND element 5 and the first input of the first group of inputs AND element 6, the output of element 9 is connected to the invert input RA 3, the second input of the first group of inputs AND and the first input of the fourth group of inputs AND element 8, the output of the inverter 3 is connected to the indicator output 17 and the second and first inputs of the second and third groups of inputs AND element 9, respectively.

The scheme works as follows. The initial state is set when a low level is applied to input 13 and a high level signal is sent to control input 14. In this case, output 16 is set to “1” (high level), and output 15 is set to “0” (low level). Recording a new state from the information input 12 to the first single-cycle trigger formed by elements 5 and 6 is provided by supplying a low level input 14. At the same time, a high logic level is formed at the output of inverter 2, which allows recording into the first one-stroke trigger and locking the second one-stroke trigger formed by elements 10 and 11. The information is transferred from the first one-stroke trigger to the second when a high signal level is applied to control input 14. In this case, the first one-stroke trigger is locked at the inputs and stores the state of its outputs, which is also transferred to the second one-stroke trigger. Elements 3, 4, 7-9 serve as an indicator of the end of transients in the D-flip-flop and as a controller of the switching phases of the D-flip-flop, while element 7 analyzes the correspondence of the state of the first and second one-cycle triggers, and element 8 indicates the correspondence of the state of the outputs of the first one-cycle trigger the value of the information input 12 and the output of the inverter 1.

In the proposed scheme, a synchronous zero setting is used: the transition of the trigger outputs to the set state is not specifically indicated. As a rule, a reset in D-flip-flops is used only to restore the trigger to its initial state immediately after turning on the power. In this case, the reset time is selected large enough to bring to an initial state all the elements of the system, of which the D-trigger is a part. Implementing a self-synchronous reset under such conditions would be redundant and hardware redundant.

The features of this scheme in comparison with the prototype are as follows.

The trigger information input is single-phase, which allows the use of a D-trigger as an interface element between synchronous and self-synchronous circuits. Trigger information outputs have paraphase (mutually inverse) coding without a spacer. Due to this, information outputs retain their significance between the moments of updating, which facilitates their use by subsequent devices. The updated indicator output captures the moment of the end of transient processes in all trigger elements, both those that were part of the prototype and newly introduced, which provides an indication of all elements in the self-synchronous circuit.

Thus, the proposed device ensures the self-synchronization of the D-trigger and the improvement of its consumer characteristics due to the single-phase information input and the paraphase information output without a spacer. The objective of the invention is achieved.

In addition, the proposed D-trigger allows you to halve the number of information links between a multi-bit source of input information and a register based on this self-synchronous D-trigger.

The concepts of "single phase" and "paraphase" are defined as follows. A signal is considered “single-phase” if it is single and requires the use of an inverter to obtain the opposite (inverse) value. “Paraphase” is a signal represented by a pair of variables (signals). In the static state, after the end of the dynamic processes of switching elements in the circuit, the two components of the paraphase signal have mutually inverse states. As a result, in a static state, the paraphase signal {X, XB} can take one of two working states: {X = 0, XB = 1} or {X = 1, XB = 0}. The transition from one static state to the opposite is carried out through the same dynamic state, {1,1} or {0,0}, determined by the type of elements that form the paraphase signal. A typical representative of a paraphase output device is a conventional synchronous cross-feedback trigger, such as an RS trigger.

Information sources

[1] Shilo V.L. Popular Digital Chips: A Guide. 2nd ed., Rev. - Chelyabinsk, Metallurgy, Chelyabinsk department., 1989 - Fig. 1.54a.

[2] Aperiodic automata. Ed. V.I. Warsaw. M .: Nauka, 1976 .-- 424 p. - Figure 2.16a.

Claims (1)

Self-synchronous D-flip-flop, containing two single-cycle flip-flops, information input, control input, zero input, direct and inverse information outputs, indicator output, characterized in that inverters at the inputs are input: information and control, the first single-cycle trigger is implemented on two elements AND-OR-NOT - the first and second, and the second one-stroke trigger is implemented on two elements OR-AND-NOT - the first and second, and also a device for indicating the end of transients in the trigger, implemented on three electric the AND-OR-NOT elements - the third, fourth and fifth, the OR-NOT element and the inverter, the information input is connected to the input of the first inverter, the third input of the first group of inputs AND the second AND-OR-NOT element, the first input of the OR-NOT element and the second the input of the third group of inputs AND of the fourth AND-OR-NOT element, the control input is connected to the input of the second inverter and the second input of the OR-NOT element, the zeroing input is connected to the second input of the second group AND of the inputs of the second AND-OR-NOT element, the output of the first inverter is connected to the first input of the first group of inputs And the first AND-OR-NOT element and the first input of the second group of inputs AND the fourth AND-OR-NOT element, the output of the second inverter is connected to the second inputs of the first groups And the first and second elements AND-OR-NOT, the second inputs of the first groups of inputs OR the first and the second element OR-AND-NOT, the input of the third group of inputs AND the third element AND-OR-NOT, the third input of the third group of inputs AND the fourth element AND-OR-NOT and the second input of the fourth group of inputs AND the fourth element AND-OR-NOT, the output of the element is NOT connected to the first input of the first group of inputs AND and the third input of the second group of inputs AND of the fourth AND-OR-NOT element, the output of the first AND-OR-NOT element is connected to the first input of the first group of inputs OR of the first OR-AND-NOT element, the first input of the second group of inputs AND of the second AND-OR- element NOT, the first input of the first group of inputs AND the third AND-OR-NOT element and the first input of the third group of inputs AND the fourth AND-OR-NOT element, the output of the second AND-OR-NOT element is connected to the input of the second group of inputs AND the first AND-OR element -NOT, the first input of the first group of inputs OR the second element OR-AND-NOT, the second the second group of inputs AND of the third AND-OR-NOT element and the second input of the second group of inputs AND of the fourth AND-OR-NOT element, the output of the first OR-AND-NOT element is connected to the inverse information output of the trigger, the input of the second group of inputs OR of the second OR element -AND NOT and the second input of the first group of inputs AND the third AND-OR-NOT element, the output of the second OR-AND-NOT element is connected to the direct information output of the trigger, the input of the second group of inputs OR of the first OR-AND-NOT element and the first input of the second groups of inputs AND the third element AND-OR-NOT, you the course of the third AND-OR-NOT element is connected to the first inputs of the first and second groups of inputs AND of the fifth AND-OR-NOT element, the output of the fourth AND-OR-NOT element is connected to the second inputs of the first and third groups of inputs AND the fifth AND-OR element NOT, the third input of the first group of inputs AND the first AND-OR-NOT element and the first input of the first group of inputs AND the second AND-OR-NOT element, the output of the fifth element AND-OR-NOT is connected to the input of the third inverter, the second input of the first group of inputs AND and the first input of the fourth group of inputs AND of the fourth AND-OR-NOT element, output t the third inverter is connected to the indicator output and the second and first inputs of the second and third groups of inputs And the fifth element AND-OR-NOT, respectively.