RU2365031C1 - Self-synchronous duple d flip-flop with high active level of control signal - Google Patents

Abstract

FIELD: physics; computer technology.

SUBSTANCE: invention concerns to pulse and computer technology and can use at construction of self-synchronous flip-flop, register and computing circuits, systems of digital information processing. This result is reached because the inverting element and four elements OR-AND-NOT are entered in the scheme containing two elements AND-OR-NOT, an information input, an operating input, direct and inverse information outputs and a display output are entered .

EFFECT: maintenance of self-synchronous realisation of the duple D flip-flop with high active level of a control signal, single-phase coding of an information input and paraphase coding of an information output.

7 cl, 8 dwg

Description

A self-synchronous push-pull D-flip-flop with a high active level of the control signal refers to pulsed and computer technology and can be used to build self-synchronous trigger, register and computing devices, digital information processing systems.

Known D-trigger [1], containing six elements AND NOT.

A disadvantage of the known device is the lack of means for indicating the end of transients.

Closest to the proposed solution by technical nature and adopted as a prototype is an RS-trigger [2], containing five AND-OR-NOT elements, with paraphase coding of information inputs and outputs and means of indicating the end of transients.

The disadvantage of the prototype is that it only works with data presented in a paraphase code, which doubles the number of information links between a multi-bit source of input information and a register based on this trigger and does not allow using it as an interface element between synchronous and self-synchronous circuits.

The problem solved in the invention is to provide a self-synchronous implementation of a push-pull D-flip-flop with a single-phase information input and a high active level of the control signal, which guarantees the operability of the trigger for any delays of its constituent elements.

This is achieved by the fact that in a trigger containing two AND-OR-NOT elements, an information input, a control input, direct and inverse information outputs and an indicator output, an inverter is introduced at the information input and four OR-AND-NOT elements, the information input is connected to inverter input, the second input of the first group of inputs OR of the first element OR-AND-NOT, the first input of the first group of inputs OR of the third element OR-AND-NOT and the second input of the second group of inputs OR of the fourth element OR-AND-NOT, the control input is connected to the input second group OR OR of the first element OR-AND-NOT, the output of which is connected to the second inputs of the first groups of inputs OR of the second and third elements OR-AND-NOT, the third input of the second group of inputs OR and the first input of the third group of inputs OR the fourth element OR-AND-NOT , to the second input of the first group of inputs AND of the first AND-OR-NOT elements and the first input of the first group of inputs AND of the second AND-OR-NOT element, the inverter output is connected to the first inputs of the first groups of inputs OR of the first and second elements OR-AND-NOT and the second the input of the third group of inputs OR the fourth element LIE-AND-NOT, the output of the second OR-AND-NOT element is connected to the second input of the first group of inputs OR and the first input of the second group of inputs OR of the fourth element OR-AND-NOT, the input of the second group of inputs OR of the third element OR-AND-NOT and the first input of the first group of inputs AND of the first AND-AND-NOT element, the output of the first AND-OR-NOT element is connected to the input of the second group of inputs AND the second AND-OR-NOT element, the first input of the first group of inputs OR of the fourth OR-AND-NOT element and the inverse information output of the trigger, the output of the third element OR-AND-NOT connected to the input of the third group of inputs OR and the first input of the fourth group of inputs OR of the fourth element OR-AND-NOT, the input of the second group of inputs OR of the second element OR-AND-NOT and the second input of the first group of inputs AND the second element AND-OR-NOT, the output of the second the AND-OR-NOT element is connected to the input of the second group of inputs AND the first AND-OR-NOT element, the second input of the fourth group of inputs OR the fourth element OR-AND-NOT and the direct information output of the trigger, the output of the fourth element OR-AND-NOT trigger indicator output.

The proposed device meets the criterion of "significant differences". The use of the elements OR-AND-NOT, AND-OR-NOT and an inverter to implement a push-pull D-trigger is known. However, their use in this case allowed to achieve the effect expressed by the purpose of the invention.

Since the introduced structural connections in similar technical solutions are not known, the device can be considered to have significant differences.

Figure 1 shows a diagram of a self-synchronous push-pull D-flip-flop with a single-phase data input and a high active control signal level.

The D-trigger circuit contains an inverter 1, four elements OR-AND-NOT 2-5, two elements AND-OR-NOT 6-7, information input 8, control input 9, direct information output 10, inverse information output 11 and indicator output 12, the information input is connected to the input of the inverter 1, the second input of the first group of inputs OR element OR-AND-NOT 2, the first input of the first group of inputs OR element OR-AND-NOT 4 and the second input of the second group of inputs OR element OR-AND-NOT 5, the control input 9 is connected to the input of the second group of inputs OR element OR-AND-NOT 2, the output of which is it is connected to the second inputs of the first groups of inputs OR elements OR-AND-NOT 3 and 4, the third input of the second group of inputs OR and the first input of the third group of inputs OR element OR-AND-NOT 5, the second input of the first group of inputs AND element AND-OR- NOT 6 and the first input of the first group of inputs AND element AND-OR-NOT 7, the inverter 1 output is connected to the first inputs of the first groups of inputs OR elements OR-AND-NOT 2 and 3 and the second input of the third group of inputs OR element OR-AND-NOT 5, the output of the element OR-AND-NOT 3 is connected to the second input of the first group of inputs OR and the first input of the second group of inputs DIV OR element OR-AND-NOT 5, the input of the second group of inputs OR element OR-AND-NOT 4 and the first input of the first group of inputs AND element AND-OR-NOT 6, the output of which is connected to the input of the second group of inputs AND element AND-OR -NOT 7, the first input of the first group of inputs OR of the OR-AND-NOT 5 element and the inverse information output of trigger 11, the output of the OR-AND-NOT 4 element is connected to the third input of the third group of inputs OR and the first input of the fourth group of inputs OR of the OR- AND-NOT 5, the input of the second group of inputs OR element OR-AND-NOT 3 and the second input of the first group of inputs And e the AND-OR-NOT 7 element, the output of which is connected to the input of the second group of inputs AND of the AND-OR-NOT 6 element, the second input of the fourth group of inputs OR of the OR-AND-NOT 5 element and the direct information output of trigger 10, the output of the OR-AND element - NOT 5 is connected to the indicator output of trigger 12.

The scheme works as follows. Recording a new state from the information input 8 into the bistable cell formed by elements 3 and 4 is provided by supplying a high level to the control input 9. The output of element 2 switches to a low state, thereby opening the inputs of the bistable cell on elements 3 and 4. If the information input 8 is low, the OR-AND-NOT 4 element will switch to state "1", and the element OR-AND-NOT 3 - to state "0". In this case, the indicator output 12 goes into state "1". With a low signal level at the control input 9, the output of element 2 switches to a high state and the bistable cell on elements 3 and 4 is locked at the inputs, maintaining the state of its outputs. In this case, the second bistable cell on the AND-OR-NOT 6 and 7 elements is unlocked at the inputs and the state of the outputs of the first bistable cell is overwritten into the second bistable cell. The status of the outputs of the trigger 10 and 11 is updated, and the indicator output 12 goes into state "0". Element 5 performs the function of an indicator of the end of transients in all elements of a push-pull D-flip-flop and a phase regulator for switching it. The value "1" at the output of element 5 indicates the end of the switching of the trigger to the working phase - the phase of fixing the value of the information input 8 at the outputs of the first bistable cell, and the value "0" indicates the end of the switching of the trigger to the spacer - the phase of storing the state of the first bistable cell and update the state of the outputs of the second bistable cell, thereby ensuring self-synchronization of its functioning.

The features of this scheme in comparison with the prototype are as follows.

The trigger information input is single-phase, which allows the use of a D-trigger as an interface element between synchronous and self-synchronous circuits. The updated indicator output captures the moment of the end of transient processes in all trigger elements, both those that were part of the prototype and newly introduced, which provides an indication of all elements in the self-synchronous circuit.

Thus, the proposed device provides self-synchronous operation of a push-pull D-flip-flop with a single-phase information input. The objective of the invention is achieved.

In addition, the proposed push-pull D-trigger allows you to halve the number of information links between a multi-bit source of input information and a register based on this self-synchronous D-trigger.

This push-pull D-flip-flop does not have the inputs of the “0” and “1” settings, which in a number of practical cases is a significant drawback. However, the proposed option is easily converted to a trigger with a preset.

Figure 2 shows a diagram of a self-synchronous push-pull D-trigger with a zero setting input 13 and a high active control signal level. The circuit differs from the circuit in Fig. 1 in that the second group of inputs OR of the OR-AND-NOT 3 element contains two inputs, the first of which is connected to the zero-setting input 13, and the second to the output of the OR-AND-NOT 4 element, as and in the circuit of FIG. 1. Zero setting is done by applying to the control input 9 low level, and at the input of the installation 13 - high level. As a result, the output of element 2 switches to the high level state, the output of the OR-AND-NOT 3 element switches to "0" (low level state), the OR-AND-NOT-4 element switches to "1" (low level state), the AND element -OR-NOT 6, which forms the inverse output of trigger 11, - in "1", and the element AND-OR-NOT 7, which forms the direct output of trigger 10, - in "0", completing the installation.

Figure 3 shows a diagram of a self-synchronous push-pull D-trigger with a unit of 13 and a high active control signal level. The circuit differs from the circuit in FIG. 1 in that the second group of inputs OR of the OR-AND-NOT 4 element contains two inputs, the first of which is connected to the installation input of unit 13, and the second to the output of the OR-AND-NOT 3 element, as and in the circuit of FIG. 1. The unit is set by applying to the control input 9 a low level ("0"), and to the input of the installation 13 - a high level ("1"). As a result, the output of element 2 switches to the high level, the output of the OR-AND-NOT 4 element switches to the state "0", the output of the OR-AND-NOT 3 element is switched to "1", the AND-OR-NOT 7 element forms a straight line trigger 10, the output is in "1", and the AND-OR-NOT 6 element, forming the inverse output of trigger 11, is in "0", completing the installation.

Figure 4 shows a diagram of a self-synchronous push-pull D-trigger with a unit and zero setting and a high active control signal level. The circuit differs from the circuit in figure 2 in that the second group of inputs OR of the OR-AND-NOT 4 element contains two inputs, the first of which is connected to the installation input of unit 14, and the second to the output of the OR-AND-NOT 3 element, as and in the circuit of FIG. 2. The setting of zero or one is carried out by the method described above. Simultaneous supply to the inputs of the zero setting 13 and high-level unit 14 is prohibited.

The described variants of a self-synchronous push-pull D-trigger with a zero and / or one setting are characterized by the fact that the installation is not self-synchronous. During the installation, the outputs of the first and second bistable cells switch, leading to a short-term uncontrolled switching of the output of the indicator element 5. In most practical cases, this turns out to be sufficient, since the installation of triggers is performed once - at the time of starting up, supplying power to the device, which uses the trigger. However, such a solution is not suitable for dynamically setting zero or one at the trigger outputs in strictly self-synchronous devices. One of the conditions for the device to belong to the strictly self-synchronous class is the requirement that there are no uncontrolled switching of elements, no “bounce” at the inputs of the elements.

Figure 5 shows a diagram of a self-synchronous push-pull D-flip-flop with a high active level of the control signal with a single-phase data input and a zero setting input, satisfying the requirements for strictly self-synchronous circuits. This trigger option differs from the circuit in FIG. 2 in that the compositions of the first and fourth groups of inputs OR are expanded in the element OR-AND-NOT 5: the third inputs connected to the zero-setting input 13 are introduced into them. Zero setting is carried out in the manner described above . But at the same time, the output of the indicator element OR-AND-NOT 5 does not change, since all its input groups are blocked by high levels at the input of setting zero 13 and the output of the element OR-AND-NOT 2. Indication of the end of the installation process of the trigger is carried out by additional logic that controls switching to "1" inverse trigger output 11.

Figure 6 shows a diagram of a self-synchronous push-pull D-flip-flop with a high active level of the control signal with a single-phase data input and unit setting input, satisfying the requirements for strictly self-synchronous circuits. This trigger option differs from the circuit in FIG. 3 in that the compositions of the first and fourth groups of inputs OR are expanded in the element OR-AND-NOT 5: the third inputs connected to the unit 13 input are entered into them. The unit is set in the way described above . But at the same time, the output of the indicator element OR-AND-NOT 5 does not change, since all its input groups are blocked by high levels at the input of unit 13 and the output of the element OR-AND-NOT 2. Indication of the end of the installation process of the trigger is carried out by additional logic that controls switching to "1" direct trigger output 10.

Figure 7 shows a diagram of a self-synchronous push-pull D-flip-flop with a high active level of the control signal with a single-phase data input and zero and one set inputs, which satisfies the requirements for strictly self-synchronous circuits. This trigger option differs from the circuit in Fig. 4 in that the elements of the first and fourth groups of inputs OR are expanded in the element OR-AND-NOT 5: the third inputs connected to the zero-setting input 13 and the fourth inputs connected to the input are introduced into them setting the unit 14. The setting of zero and one is carried out by the method described above. But at the same time, the output of the indicator element OR-AND-NOT 5 does not change, since all its input groups are blocked by high levels at the input of setting zero 13 (or units 14) and the output of the element OR-AND-NOT 2. Indication of the end of the installation process of the trigger is additional logic that controls switching to “1” the direct output of trigger 10 (when setting a unit) or switching to “1” of the inverse output of trigger 11 (when setting zero). Simultaneous supply to the inputs of the zero setting 13 and high-level unit 14 is prohibited.

On Fig shows a diagram of a self-synchronous push-pull D-flip-flop with a high active level of the control signal with a single-phase data input and phase output 13 connected to the output of the element OR-AND-NOT 2. The phase (initiating the phase of the D-trigger) communication output is used to accelerating the response of the device-source of the information signal: permission to switch to the opposite phase of operation is issued immediately as soon as the OR-AND-NOT 2 element in the trigger switches after a new value arrives at control input 9, without waiting for windows Ania switching the remaining elements in the trigger circuit. A similar output can be used in all other versions of the D-trigger described above.

Information sources

[1] Shilo V.L. Popular Digital Chips: A Guide. 2nd ed., Rev. - Chelyabinsk: Metallurgy, Chelyabinsk Department., 1989 .-- Fig. 1.50 (a).

[2] Astakhanovsky A.G., Warsaw V.I., Marakhovsky V.B. and other aperiodic automata. // Ed. V.I. Warsaw. - M .: Nauka, 1976, - Fig. 2.16 (b).

Claims (8)

1. A self-synchronous push-pull D-flip-flop with a high active level of the control signal, containing two AND-OR-NOT elements, an information input, a control input, direct and inverse information outputs and an indicator output, characterized in that an inverter at the information input and four elements OR-AND-NOT, the information input is connected to the inverter input, the second input of the first group of inputs OR the first element OR-AND-NOT, the first input of the first group of inputs OR the third element OR-AND-NOT and the second input of the second group of inputs OR of the fourth element OR-AND-NOT, the control input is connected to the input of the second group of inputs OR of the first element OR-AND-NOT, the output of which is connected to the second inputs of the first groups of inputs OR of the second and third elements OR-AND-NOT, the third input of the second group of inputs OR and the first input of the third group of inputs OR of the fourth element OR-AND-NOT, the second input of the first group of inputs AND the first element AND-OR-NOT and the first input of the first group of inputs AND the second elements AND-OR-NOT, the inverter output is connected to the first inputs first groups of inputs OR first and second e of OR-AND-NOT elements and the second input of the third group of inputs OR of the fourth element OR-AND-NOT, the output of the second element OR-AND-NOT is connected to the second input of the first group of inputs OR and the first input of the second group of inputs OR of the fourth element OR-AND- NOT, the input of the second group of inputs OR the third element OR-AND-NOT and the first input of the first group of inputs AND the first element AND-OR-NOT, the output of the first element AND-OR-NOT connected to the input of the second group of inputs AND the second element AND-OR- NOT, the first input of the first group of inputs OR of the fourth element OR-AND-NOT and inverse and with the trigger information output, the output of the third OR-AND-NOT element is connected to the third input of the third group of inputs OR and the first input of the fourth group of inputs OR of the fourth element OR-AND-NOT, the input of the second group of inputs OR the second element OR-AND-NOT and the second input the first group of inputs AND of the second AND-OR-NOT element, the output of the second element AND-OR-NOT is connected to the input of the second group of inputs AND the first element AND-OR-NOT, the second input of the fourth group of inputs OR the fourth element OR-AND-NOT and direct trigger information output, fourth e output The OR-AND-NOT element is connected to the indicator output of the trigger. 2. A self-synchronous push-pull D-flip-flop with a high active level of the control signal according to claim 1, characterized in that a zero-setting input is entered into it and the second group of inputs OR of the second element OR-AND-NOT has two inputs, the first of which is connected to the input zero, and the second input is connected to the output of the third element OR-AND-NOT. 3. The self-synchronous push-pull D-flip-flop with a high active level of the control signal according to claim 1, characterized in that the unit setting input is entered into it and the second group of inputs OR of the third element OR-AND-NOT has two inputs, the first of which is connected to the input installation unit, and the second input is connected to the output of the second element OR-AND-NOT. 4. A self-synchronous push-pull D-flip-flop with a high active level of the control signal according to claim 2, characterized in that the unit setting input is entered into it and the second group of inputs OR of the third element OR-AND-NOT has two inputs, the first of which is connected to the input installation unit, and the second input is connected to the output of the second element OR-AND-NOT. 5. A self-synchronous push-pull D-flip-flop with a high active level of the control signal according to claim 2, characterized in that in the fourth OR-AND-NOT element the third inputs to the first and fourth groups of OR inputs connected to the zero-setting input are entered. 6. Self-synchronous push-pull D-flip-flop with a high active level of the control signal according to claim 3, characterized in that in the fourth element OR-AND-NOT introduced third inputs in the first and fourth groups of inputs OR connected to the unit installation input. 7. Self-synchronous push-pull D-flip-flop with a high active level of the control signal according to claim 4, characterized in that in the fourth element OR-AND-NOT introduced the third and fourth inputs to the first and fourth groups of inputs OR, and the third inputs of these groups are connected to the input is set to zero, and the fourth inputs of these groups are connected to the input of the unit. 8. A self-synchronous push-pull D-flip-flop with a high active level of the control signal according to any one of claims 1 to 7, characterized in that a communication phase output connected to the output of the first element OR-AND-NOT is introduced into the circuit.

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