RU2130692C1 - Timer - Google Patents

Abstract

FIELD: control equipment, telemetry, instruments, computer engineering, communication devices. SUBSTANCE: device has single-tick D flip-flop 3, which is controlled by AND, OR and NOT gates (2, 1, 6), and delay line 4, which is designed as diode 5 and RC circuit. EFFECT: possibility to delay output signal of given duration upon arrival of pulse input signal. 1 dwg

Description

 The invention relates to timing devices and may find application in control systems, monitoring, measurement, computing devices, communication devices of various industries.

 A known timer is described, for example, in [1], containing a binary pulse counter and a decoder with many outputs. The disadvantages of such a device include the need for additional installation of an external pulse generator and a key that allows you to control the operation of the device with a pulse control signal.

 It is also known a device described, for example, in [2], containing a D-flip-flop, whose inverse output is connected to the output bus, and an even number of elements NOT, as well as an additional D-flip-flop and the And element with an operating mode control bus. The disadvantages of such a device include the need for additional installation of a foreign key that allows you to control the operation of the device with a pulse control signal.

 As a prototype adopted the device described in [2].

 The aim of the present invention is to expand the functionality, namely the possibility of generating a signal of a given duration with a pulse control input signal.

 This goal is achieved by the fact that a delay line, a diode and an OR element are additionally introduced into the device to control the trigger.

 The invention is illustrated in the drawing, which shows a timer circuit.

 Device Input B / FIG. 1 / is connected to the first input of the two-input element OR 1, the output of which is connected to the first input of the two-input element AND 2, the output of which is connected to the input D of the single-cycle D-trigger 3, connected via the delay line 4 to the clock input C. Direct output Q of the D-trigger 3 connected to the second input of the OR element 1, the output of the device and the anode of the diode 5, the cathode of which is connected to a resistor R connected to the capacitor C, the second side of which is connected to the common minus of the power source, and the input of the element HE 6, the output of which is connected to the second input AND gate 2. The capacitor C and resistor R are chosen from the condition of providing a predetermined time delay. Resistor R can be variable to set the time delay.

 The use of a delay line, a diode, and an OR element to control a trigger in the sources was not detected.

 The device operates as follows. In the initial state, the D-flip-flop is in the off state (zero state of the direct output and unit inverse /, and the capacitor C is discharged. At the output of the element NOT 6 there is a single signal. There is no signal at the output of the device’s output. Upon receipt of a short-term control / switching / signal at the input of the device input, it is supplied to the first input of the OR 1 element and from its output to the first input of the And 2 element, from the output of which it goes to input D of trigger 3, and through the delay line 4 to its input C. The trigger is switched on in the single state of direct output Q and the zero inverse output Q and is blocked in this state. A single signal from direct output Q is fed to the output of the device’s outputs and to diode 5. The process of charging the capacitor C through the resistor R and counting the delay time of the signal at the output of the device’s output begins. After the control signal ends, the on state of trigger 3 is maintained by supplying a single signal from its direct output Q to the second input of the OR element 1 and through the And 2 element to the input D of the trigger. After charging the capacitor C to the level of a single signal and after inverting the element NOT 6, the zero signal is fed to the second input of the element And 2 and the input D of trigger 3. Trigger 3 is turned off, a zero signal appears at its direct output Q. The output signal at the output of the output of the device ends.

 Diode 5 is necessary to eliminate the discharge current of the capacitor to the load, distorting the duration of the output signal.

Literature
1. Biryukov S. A. Digital devices on integrated circuits. M .: Radio and communications, p. 73, fig. 103.

 2. USSR author's certificate N 1718368, cl. H 03 K 5/01, 1992

Claims (1)

 A timer containing input and output, a D-trigger, an AND element, a NOT element, characterized in that a delay line, a diode and an OR element are inserted into it, the device input is connected to the first input of the OR element, the output of which is connected to the first input of the AND element, the output of which is connected to the D-input of the D-trigger connected via a delay line to its C-input, the direct output of the D-trigger is connected to the second input of the OR element, the output of the device and the anode of the diode, the cathode of which is connected to a resistor through which the charging process capacitor, second side which it is connected to the common minus of the power source, and the input of the element NOT, the output of which is connected to the second input of the element I.