RU209U1 - Statistical analyzer of the conditional distribution function of the range of voltage fluctuations - Google Patents

Abstract

Statistical analyzer of the conditional distribution function of the range of voltage fluctuations, containing an analog-to-digital converter, first, second and third registers, first and second comparison schemes, first, second, third, fourth, fifth and sixth shapers, first, second, third and fourth elements NOT, first, second and group of elements NOT, element AND, first and second triggers, clock, monitoring counter, binary counter, pulse distributor, random access memory, binary decimal counter ik, an AC to DC converter, the input of which serves as the input of the analyzer, and the output is connected to the input of an analog-to-digital converter, the information output of which is connected to the information input of the first register and to the first input of the first comparison circuit, the output of the first register is connected to the second input of the first circuit comparison, the outputs of which are connected to the inputs of the first and second formers, the outputs of which are connected to the inputs of the third element AND NOT and to the installation inputs of the first trigger, the outputs of which are inens with inputs of the third and fourth shapers, the outputs of which are connected to the first and second inputs of the fourth element AND NOT, the third input of which is connected to the output of the sixth shaper, the input of which is connected to the output of the control counter, the counting input of which is connected to the output of the clock generator, the fourth output AND element is NOT connected to the zero counter input of the binary counter, the counting input of which is connected to the output of the third AND element, NOT, whose output is also connected to the zero counter input of the control counter and

Description

STATLST FIELD THE ANALYZER HAS CONDITIONED THE FUNCTIONAL EXTENSION 1SHVNL. 1 SIZE 013 К01ББАНЕЙЛ ПП.-ШНЛЛ

The proposed utility model relates to: computing and information-measuring technology and can be used to control the quality of electricity in electric networks of power systems and industrial enterprises.

Known vibration analyzer 1j, containing an analog-to-digital converter, registers, subtraction blocks, block otchitiya: s, distributor / level, block. IJ codes, a clock generator, a unit for determining the direction and duration of changes are compared.

The disadvantages of the prototype are the complexity and bulkiness of its circuit, as well as the low reliability of the analyzer.

There is also a well-known statistical analyzer of the conditional j yHK distribution of the amplitude of the voltage fluctuations 2, comprising an AC to DC converter, analogous to qi; core converter, registers, equalization circuit, counters, random access memory, shapers. triggers, IDL elements, AND element, NOT element, rectangular pulse generator, level distributor.

The disadvantage of the analyzer is the low accuracy of information processing, due to the presence of only two levels of signal quantization for each analyzer memory signal and the lack of blocking of entering the memory into the analyzer memory when the binary counter is full, as a result of which false information is stored in the analyzer's memory.

) close to the proposed technical solution is a statistical analyzer of the conditional distribution function of the ranges of voltage fluctuations e, containing an AC to DC converter, an analog-to-digital converter, comparison circuits, resistors, impulse, oscillator and I-HS elements, NOT elements, triggers, control counter, binary counter, random access memory, binary-decimal counter, clock generator, level distributor.

The disadvantages of the analyzer are: a) the need to use an external clock device to measure and the appearance of an additional error in the processing of information in the analyzer due to the non-simultaneity of time instants, the start of the measurement clock of the clock device and zeroing the analyzer memory;

b the inability to observe the current value of the range of voltage fluctuations in the investigated part.

The goal of presumptive grinding of the polyesic model is: a) to increase the usability of the device;

b) improving the accuracy of information processing in the analyzer;

c) the expansion of the functional possibilities of analysis, -. a.

This goal is achieved by the fact that in a statistical analyzer the conditional distribution function of the span is fluctuated; for the voltage, it contains the analog-to-digital converter, the first, second and third registers, the first and second spawn circuits, first, second, third, fourth, fifth and the second form, whether the first, second, third, and fourth elements are Y-NOT, the first, second, and the group of elements P, the element I, the first and second triggers, the clock generator, control counter, binary counter, pulse distributor, opsitive memo device, binary-decimal counter, n: alternating voltage to constant voltage selector, the input of which serves as the input of the analyzer, and the output is connected to the input of an analog-to-digital converter, the information output of which is with the first input of the first register and with the first input of the first comparison circuit, the output of the first the register is connected to the second input of the first comparison circuit, the outputs of which are connected to the inputs of the first and second formers, the outputs of which are created with the inputs of the third element L-HS and with the inputs of the installation of the first flip-flop, the outputs of which are connected to the inputs of the third and fourth -formirovateley whose outputs are connected to first and second inputs .; the fourth element AND NOT, whose third input

connected to the output of the sixth shaper, the input of which is connected to the output of the control signal 1ka, the counting input of which is connected to the output of the clock generator, the output of the fourth element I-NOT is connected to the zero-setting input of the binary counter, the counting input of which is connected to the output of the third AND-NOT element the output of which is also created with the input of setting the zero of the control counter and with the input of the first element Ni, the output of which is connected to the recording input of the first control) a, the second output of the binary counter is connected to the first input of the second of the second element i-HB, the second / i input of which is connected: n to the output of element 1, the inputs of which are connected to the outputs of the elements NOT, the inputs of which are connected to the senior outputs of the binary counter, the senior outputs of which are also connected to the first input of the second comparison circuit and to the information the input of the second and third registers, the output of the third register is connected to the second input BTOpOii of the comparison circuit, the output of which is connected to the input of the second HB element, the output of which is connected to the first input of the first I-HiS element, the second input of which is connected to the output the ode of the second element H-HS, and the output is connected to the input of the start of the fifth shaper, the direct output of which is connected to the recording input of the second raglstra, and inv; the lower output of the fifth linker is connected to the recording input of the third register and to the installation input of the second trigger unit, the inverse output of which is connected to the installation input to the initial state of the pulse distributor, the counting input of which is connected to the output of the clock generator, the first and second outputs of the pulse distributor are connected respectively to the recording input and with the counting input of the binary decimal counter, the third output of the pulse distributor is connected to the recording input of random access memory a, the output of which is approaching: it is connected to the information path of the binary decimal counter, the output of which is connected to the information input of the operational memory, the address input of which is connected to the output of the second register, the fourth output of the pulse distributor is connected to the input of the zero setting of the second trigger, the fourth the register, the fifth element of the I-NC, the first and second dvuhsyfory, the first and second indicators, timer-clock, multiplexer.

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the seventh shaper, the switch, the on / off button, the logo is connected to the input of zeroing the RAM and the timer-clock, the output of which is connected to the first input of the multiplexer, the second input of which is connected to the output of the binary-decimal counter, the switch is connected to the control input of the multiplexer, the output of which is connected to the input of the second decoder, the output of which is connected to the second indicator, the high-order output of the binary counter is connected to the information input of the fourth register, the input is and which is connected to the input of the fifth AND-NOT element, the inputs of which are connected from the outputs of the third and fourth forms, the output of the fourth register is connected to the input of the first decoder, the output of which is created with the input of the first indicator, the output of the fourth I-HS element is connected to the input of the seventh shaper, the output of which is connected to the input of the zeroing binary counter.

The essence of the proposed useful model is illustrated by the drawing, where na, | П1Г.1 shows a diagram of the device, and figure 2 - graphs of changes nap; can be found on the elements of the device.

The analyzer is made l-channel L - the number of levels of analysis equal to the number of bits of the desired distribution function of the amplitude of the voltage fluctuations). Statistical information is accumulated in random access memory, access to which is carried out using its address input, which has /. In binary digits, the latency of each analyzer memory channel is equal. To exchange information between random access memory and a binary-decimal counter, a group ring communication is organized, which has 4 x W binary digits. The device uses an / V-bit (where / / -i / G, moreover) a parallel analog-to-digital converter. The capacity of the second, third and fourth register is equal to L, the group element does NOT invert -2 single signals, respectively, the element AND is) input. The first and second comparison schemes veoR d 4Got "y

corresponding data / bit information.

Upon further consideration .; the algorithm of the device, as an example, take l "16, 4,,,.

;

mfff

For example, at constant 1, the input of which serves as the input of the analyzer, and the output is connected to the input of the analog-to-digital converter 2, the information output of which is connected with the first input of the first comparison circuit 3 and with the information input of the first register 4, the output of which is connected to the input of the first comparison circuit 3 the outputs of the rotor are connected with the inputs of the first and second shapers 5 and 6, the outputs of which are connected to the inputs of the third element I-Nd 7 and with the inputs set the first trigger b, the outputs of which are connected to the inputs of the third and In addition, the controllers 9 and 10, the outputs of the lots are created with the input; the first and second inputs of the fifth element L-HS il and the first input l of the second inputs /, the fourth element I-Ny 12, TpJT, whose bi input is connected with the output shasto shaper 13, the input of which is connected to the output of the control counter 14, the input of which is connected to the output of the clock pulse generator 15, the output of the fourth element 12 is connected to the input of the seventh formatting 16, the output of which is connected to the input zero setting of the binary counter 17, the output of the third element I-NZ 7 created with a counting input dv counter 17 with the input of setting the counter zero. from control 14 and with the input of the first elemngling NL 16, the output of which is connected to the input braided of the first pjrncTpa h, the second output of the binary counter 17 is connected to the first input of the second element I-NC 19, the second input of which connected with the output of AND element 20, the inputs of which are connected; they are with the outputs of the group of elements Hii 21. whose inputs are created with the senior outputs of the binary counter; 17, the senior outputs of which are also connected to the second input input second of the comparison circuit 22 and to the input-second inputs of the second, third, fourth registers 23, 24, 25, the third register output is connected to the second input of the second comparison circuit 22, the output of which is connected by an element NOT 26, the output of which is created with the direct input of the first element L-NOT 27, the second / 1 input of which is connected with the output of the second element-i4-tt 27, the second input is icoTOpOf4) С09dine1-e - the output of the second olomont L-НЗ 19, the output the first element of L-HE 27 created w with the launch of the fifth ormrovatel 28, p direct /: the output of which is connected to the input of the second register; and 23, and the inverse output is connected to the input of the third register 24 and connected to the input of the second trigger 29, the output of which is connected to the installation input in the initial state, pulse distributor 30, s are even. 1, the input fcoTOporo is connected to the output of the galt pulse generator 15, the first and second outputs of the pulse distributors 30 are connected to the input nwcH and to the C46THJM binary decimal counter 1n.a 31, the third output of the pulse distributor is connected to the recording input of the random access memory 32, connected to the information input of the decimal decimal frequency, and 31, the output of which is connected to the information input of the random access memory 32, the address input of which is connected to the output of the second register 23 , the fourth output of the pulse distributor 30 is connected to the zero setting input of the second trigger 29, the iCHonica zero setting 33 is connected to the zeroing input of the random access memory 32 and to the zeroing input of the talmzra-clock, the output of which is connected to the torn input of the multiplegssor 35, the second input of which is under .decided to the output of the binary decimal counter 31, pz / zk: the switch 36 is connected to the control input of the multiplexer 35, the output of which is connected to the input of the second cheap switch 37, the output of which is connected to the second indicator 38, the output is About the element L-NOT II is connected to the input of recording 14 of the open register 25, the output of which is connected to the input of the input; first, bypass (4) of the rotor 39, the output of which is connected to the input of the first indicator 40.

Before starting work, it is necessary to reset the contents of random access memory 32 and the analyzer Talmzra-34 hours, for which it is necessary to press the reset button 33.

The analyzer works as follows. 3 of the analysis, the voltage of the transducer I Ui is supplied to the input of an analogue 4) pre-isolator 2, inside of which Denmark is located / i at the moment of investigation of the pressure;

For example, at time t.- t, at which the input voltage reaches its extreme (minimum value, in regiotrz 4, the number OOOOII is stored. With a further change in voltage, it crosses I, lg.2) the boundary between the third and fourth digits of analog-to-digital converter 2 At the output of the analog-to-digital converter 2, the number 000100 appears, which is larger than the number of OOOOII stored in this register in register 4. As a result, at the first output of the first comparison circuit 3, a unit voltage appears, which is supplied by the formulator 5. The latter, by its output negative pulse, transfers trigger 8 from a single state to zero, as well.

Using the first element, the I-HS 7 element was updated, the contents of the control counter 14 (hereinafter, the same resetting of the contents of the control circuit 14 is repeated at each of the points of the steamer / live voltage b across the discharge boundaries of the analog converter 2. Appearing the output of the first trigger 8 is a single starting voltage from the third driver 10, the negative output i4 pulse of which passing through the fifth and fourth elements of NAND 11,12 and being converted into a single one, goes to the inverse input of the 4-ohm the arrester 16 and the recording input of the fourth register 25. The leading edge of this pulse records the value of the first four bits of the binary counter 17 to the fourth register 25. Then, along the back; the front of the lamp from the output of the fourth element of Н-НВ 12, the seventh driver 16 and according to the predetermined term), the binary pulse counts are reset to zero from the output of its output 17. After that, on the trailing edge of the ending pulse from the output of the third element AND-NOT 7 i-Ig.2; on uzz 1g1chaEaets the contents of binary counter 17, it becomes ,, aans,. {000001. At the same moment, the number OOOIOC starts to float from the output of the analog-to-digital converter 2 of the first block 4, which evens out the moves at the first and second inputs of the first circuit Comparison 3 and, accordingly, removes the unit tension from its P31) output.

With a further increase in voltage, I 17 again C at point 2, Fig. 2, the first driver 5 starts. 3 In this case, the output pulse of the third AND-NOT 7 element increases the content of the binary counter by 17, and it becomes equal to 000010. Appears at the output the second discharge of the two-phase readout; ca 17 a single signal is applied to the first input of the second I-NC element 19, to the second input of which a unit voltage is applied from the output of the And element 20. As a result, the output of the first

rjr UT A / C.

of the I-NO 27 element is a single start; the shaper is on the base 28. The pulse from the direct output of the fifth shaper 28 writes the OSYO code from the outputs of the four high-order bits of the binary counter 17 to the second register. The pulse of the inverse output of the fifth shaper 26 is the unit state is second trigger 29, and also writes code 0000 to the third register 24. Trigger 29, turning into a single state, removes the unit voltage from the zero setting input of the 30 level distributor, as a result, it starts scanning the outputs of the last single control signal. At time t 2, the next pulse of the clock generator 15 is transferred by the distributor 30 in the compost, with liOTOpOM the unit voltage appears on its second output, connected to the recording input of the binary-decimal counter 31. In this case, the binary number is stored in the binary decimal counter 31 the result of the previous analysis and stored in the random access memory 32 at the address of the first .channel of the analyzer 0000.

At the next time, it is activated; 1 and divided for 30 hours at time tj) on the third output of the latter, connected with the counting input of the binary decimal counter 31, a pulse appears, which increases the contents of the counter by one.

At the next actuation of the distributor 20Sv, the instant of time t /,), the unit voltage appearing on its fourth output controls the writing of 32 hp of the decimal-decimal count to the RAM memory; tch: and 31 at the same address 0000 increased by one number.

The appearance at the time t of a single voltage pulse at the fifth output of the distributor 30 results in: setting; e of the second Trigger 29 to the zero state, as a result of which the distributor 30, in its order, is set to zero, a unit voltage appears at its first output, which remains free.

When the voltage rises further (L, to be exact 3, the binary counter 17 reacts again, its contents increase by one; L becomes equal to 000011, and into 4 the contents of the binary counter; 1: a 17 becomes 000100. In this case, the code from the outputs of the four high-order bits OjOI binary code 17, attached to the first input of the second comparison circuit 22. becomes larger than the code 0000 applied to its second input from the output of a third of its register 24. As a result, at the first output of the second 1 of the comparison circuit 22, a unit voltage appears, which, after passing h -Zrzz BTopo. i element HB 26 and the first element Y-NOT 27, starts the heel shaper 28. The pulses from the outputs of the fifth shaper 28 control the writing of the code 0001 from the outputs of the binary counter 17 to the second register 23, as well as the second trigger 29 is thrown into a single state. As a result, the distributor 30 comes into operation, exercising on a time interval

3 MOM 3HT time tg voltage i reaches its maximum value. Dalze, when the voltage curve I7f T04ivH 5 was crossed, the output to Ва1ход9 of analogous АИ4) equal П; 00бра:; of the gate 2 becomes less soda stored in the first step 4, as a result, on the second output of the circuit 3 appears 9-day voltage, by the end to the front of which SECURITY 4 is triggered b, LATER, with its INPUT Reflex pulse, REDUCE trigger trigger 6 from the zero state in units / xP /. counted the controls 14. Appear; esyayana on the direct output of the p-erv trigger 6 unit apryazhenie zapus.-Saet ormlrovatel 9, the output gsotorogo negative pulse passing through pyatogl and fourth elements W-HTi 11,12 and transformations; Going into a single input, the input of the seventh shaper 16 enters HHBJI.CHIIH and the input braids the fourth register 25. The leading four bits of the binary count are fused along the front of the pulse. ; and 17 t-soda which corresponds to the maximum value of the input voltage 6, AOCTHrHyTOH | f-on the t / Sat time interval in the open register 25. With. this digital code is highlighted ;. the first 11ndi: atator 40, will correspond to the current value of the stress variation. After that, on the back front for the starting pulse from the output of the third element of L-HE 7, the content of binary count 17 increases by one, it becomes equal to 00000I.

After this, the process is repeated, similar to that described on the Internet; time t.

3 points: -: an oscillation of the voltage across the time interval between the i-t tg binary binary counts, counting three pulses from the output of the third H-H element: i 7. The time interval is counted. U (t) LMZZT flat slope with creep water equal to zero. However, two voltage changes in the intervals tg-t7 and tp grow-1), the analyzer loses one sole-channel for the interval tg - tp, since the time interval between points 6 and 7 is less than the critical value 4С / and, therefore, the average derivative by this interval is greater than 1; / with.

On gentle slopes, n: rive A (/, having Ui (tf 1 / о / С

for example, at the tg -) part, the username of the binary counter 17 passes to state 000001 (at the moment of crossing the left 1 Cfft / discharge boundaries of the analog of the digital transformer 2; it was reset to zero (after the total control counter 14 chores atre At). As a result, the information is plotted on the plot;; ah into the operative memory 32, but it happens.

This is the way to accumulate in formulas by analyzing the range of voltage cholebanil - n is the voltage increase between adjacent E1stromumaml ill between E: stromumM1 l ff, og-: (that is, having a modulus of the derivative of the Manse voltage 1% / Q} of voltage parts longer than L 10 ms or between the lower gently sloping sections with a duration of more than At / j with an average CicopocTH of the voltage change of more than 1 / t / s.

At the same time, during 1 oscillation of voltage per unit, the content of the device’s channels increases, the numbers of which correspond to the number of voltage cross-cutting Uf in the process of changing sufficiently quickly the discharges of the analog-to-digital converter: 2: when the second or third grande increases, the content of the first channel increases with the address 0000, when the fourth and seventh guanders are perused, the contents of the first and second channels with addresses 0000 and 0001 increase, and when crossing the eighth to eleventh borders, it increases from contents of the first three channels with addresses 0001 and 0010, etc. . {Roma addition in the course of everyone; fluctuations before the next, in the third register 25, the code is recorded and stored corresponding to the previous value of the voltage fluctuation.

After the end of the time, T was changed, visually visible from the second indicator 36, the switch 36 opens and cuts: on the other hand, through the multiplexer 35, information from the outputs of the binary decimal counter 31, which corresponds to the contents of the selected analyzer channel, is passed through.

Based on the contents of the operational storage device 32, the dependence of the ranges of the voltage fluctuations on their average Heii of the frequency of exceeding the analysis level is constructed, by comparing which with a similarly / curve, it is concluded that the voltage fluctuation in the network is inadmissible.

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A

Prziuszveszgwami n,; in favor of a useful model compared to the well-known models is: a) increased ease of use due to the introduction of 34 general clock into the analyzer structure. for opera 1vnogo storage device 32

and the button clock-timer reset to 36;

6) improving the accuracy of oborot.i in ormacil due to the accurate counting of the time of the measurements made, due to the simultaneous zeroing of the telmera-clock 34 and the opsromnaya memory device. Svga 32;

to expand the functional capabilities of the analyzer by introducing into the analyzer structure the fifth element I-NOT II of the register 25, the first decoder 39 l of the first indicator 40, providing observation of the current value of the fluctuating voltage.

Claims (1)

Statistical analyzer of the conditional distribution function of the range of voltage fluctuations, containing an analog-to-digital converter, first, second and third registers, first and second comparison schemes, first, second, third, fourth, fifth and sixth shapers, first, second, third and fourth elements NOT, first, second and group of elements NOT, element AND, first and second triggers, clock, monitoring counter, binary counter, pulse distributor, random access memory, binary decimal counter ik, an AC to DC converter, the input of which serves as the input of the analyzer, and the output is connected to the input of an analog-to-digital converter, the information output of which is connected to the information input of the first register and to the first input of the first comparison circuit, the output of the first register is connected to the second input of the first circuit comparison, the outputs of which are connected to the inputs of the first and second formers, the outputs of which are connected to the inputs of the third element AND NOT and to the installation inputs of the first trigger, the outputs of which are inens with inputs of the third and fourth shapers, the outputs of which are connected to the first and second inputs of the fourth element AND NOT, the third input of which is connected to the output of the sixth shaper, the input of which is connected to the output of the control counter, the counting input of which is connected to the output of the clock generator, the fourth output AND element is NOT connected to the zero counter input of the binary counter, the counting input of which is connected to the output of the third AND element, NOT, whose output is also connected to the zero counter input of the control counter and with the input of the first element NOT, the output of which is connected to the input of the first register entry, the second output of the binary counter is connected to the first input of the second element AND NOT, the second input of which is connected to the output of the element AND, the inputs of which are connected to the outputs of the group of elements NOT, the inputs of which are connected to the senior outputs of the binary counter, the senior outputs of which are also connected to the first input of the second comparison circuit and to the information input of the second and third registers, the output of the third register is connected to the second input of the second circuit input, the output of which is connected to the input of the second element NOT, the output of which is connected to the first input of the first element AND-NOT, the second input of which is connected to the output of the second element AND NOT, and the output is connected to the start input of the fifth driver, the direct output of which is connected to the recording input the second register, and the inverse output of the fifth driver is connected to the recording input of the third register and to the installation input of the second trigger unit, whose inverse output is connected to the installation input to the initial state of the pulse distributor, the input of which is connected to the output of the clock generator, the first and second outputs of the pulse distributor are connected respectively to the recording input and to the counting input of the binary decimal counter, the third output of the pulse distributor is connected to the recording input of random access memory, the output of which is connected to the information input of the binary decimal counter, the output of which is connected to the information input of random access memory, the address input of which is connected to the output of the second register, the fourth output of the pulse distributor is connected to the input of the zero setting of the second trigger, characterized in that, in order to improve ease of use, improve the accuracy of information processing and expand the functionality of the analyzer, it additionally introduces a fourth register, the fifth element AND-NOT, the first and second decoders, first and second indicators, timer-clock, multiplexer, seventh driver, switch, reset button, which is associated with the zero input of random access memory and that timer, the output of which is connected to the first input of the multiplexer, the second input of which is connected to the output of the binary decimal counter, the switch is connected to the control input of the multiplexer, the output of which is connected to the input of the second decoder, the output of which is connected to the input of the second decoder, the output of which is connected to to the second indicator, the high-order output of the binary counter is connected to the information input of the fourth register, the recording input of which is connected to the output of the fifth element AND NOT, the inputs of which are connected to the output the odes of the third and fourth shapers, the output of the fourth register is connected to the input of the first decoder, the output of which is connected to the input of the first indicator, the output of the fourth element AND-NOT is connected to the input of the seventh shaper, the output of which is connected to the input of zeroing the binary counter.