RU2024184C1 - Digital filter - Google Patents

Abstract

FIELD: radio engineering. SUBSTANCE: digital filter has K filtering channels 7-1 through 7-K each incorporating three AND-gate units 1, 2, 3, OR-gate unit 4, adder-subtracter 5, and result register 6, as well as it has mode flip-flop 8, pulse characteristic register 9, interrogation register 10, and reset register 11. Digital filter affords time-variable zeroing of adder-subtracter in each filtering channel before arrival of first weight factor of pulse characteristic. EFFECT: enlarged functional capabilities. 3 dwg

Description

 The invention relates to radio engineering, in particular to devices for digital filtering of radar signals, and can be used to isolate signals from interference.

 Known FIR filters of direct, cascade and parallel forms, consisting of delay elements, multipliers and adders.

 The disadvantages of the known filters are the low speed and the inability to process real-time wideband signals.

 An adaptive filter is also known, comprising a sampling unit, a whitening filter, consisting of a series-connected auto-compensator, a slave filter, an expected signal source, a multiplication unit, and rationing units.

 The disadvantages of this device is the functional complexity and low speed.

 The closest in technical essence to the proposed one is a digital filter containing a filtering channel, consisting of a series of connected first block of AND elements, the first input of which is the first input of the filtering channel, block of OR elements, adder-subtractor and register, the output of which is connected to the second input of the adder a subtractor and with the first input of the second block of AND elements, the output of which is the output of the filtering channel, and the third block of elements AND, the first input of which is the second input of the filter channel radios, the second input is combined with the second input of the first block of AND elements and with the third input of the adder-subtractor and is the third input of the filtering channel, as well as a block of elements NOT, N-1 filtering channels identical to the first, in each of which a delay element is input which is combined with the second input of the second block of AND elements and is the fourth input of the filtering channel, and the output is connected to the installation input of the register, as well as a block of delay elements, an impulse response register, a polling register, and a mode trigger, while the moves of the block of delay elements and the block of elements are NOT combined and are the input of a digital filter, the output of the block of delay elements is connected to the first input of the j-th filter channel (where j = 1,2, ..., N), the output of the block of elements NOT is connected to the second input of the jth filtering channel, the first input of the impulse response register is combined with the first input of the polling register and connected to the direct output of the mode trigger, the second input is combined with the second input of the polling register and connected to the inverse output of the mode trigger, the third input is combined with the third input of the register the polling and the first input of the mode trigger and is the input of the clock signal, the fourth input is the input of the impulse response signal, the jth output is connected to the third input of the jth filtering channel, the fourth input of which is connected to the jth output of the polling register, the fourth input of which is the input of the polling code, and the second input of the mode trigger is the input of the mode setting signal.

 The disadvantage of the filter is its narrow functionality, due to the inability to process signals of various durations.

 The purpose of the invention is the expansion of the functionality of the filter.

 This is achieved by the fact that in a digital filter containing a block of elements NOT and a block of delay elements, the inputs of which are combined and are the input of a digital filter, a mode trigger, K filter channels, each of which contains three blocks of AND elements, a block of OR elements, an adder-subtractor and a result register, impulse response and polling registers, the first, second and third inputs of which are combined and connected respectively to the direct and inverse outputs of the mode trigger and the input of the clock signal, which is also connected to the first the mode trigger, the fourth input of the impulse response register is the input of the impulse response, and its jth direct and inverse outputs are connected respectively to the control input of the first and second blocks of elements of the jth filtering channel (j = 1 ... K), to the control input of the third block of elements And of which the jth output of the polling register is connected, the fourth input of which is the input of the polling code, the second input of the mode trigger is the input of the mode setting signal, the outputs of the blocks of delay elements and elements are NOT connected to the information inputs of the second and first blocks of AND elements of all filtering channels, within the jth filtering channel, the outputs of the first and second blocks of AND elements are connected to the inputs of the block of OR elements, the output of which is connected to the first inputs of the adder-subtractor, to the input of the least significant bit of which the jth direct output of the impulse response register is connected, and to the second inputs is the output of the result register, also connected to the information inputs of the third block of AND elements, the output of which is the output of the ph Filtration, the outputs of the filtering channels are combined to form a MOUNTING OR block, the output of which is the output of a digital filter, a reset register is entered, the outputs of which are connected to the zero input of the register of the corresponding filtering channel, information inputs are connected to the corresponding outputs of the mode trigger, the clock input is a clock input signal, and the recording input is the input of the reset code.

 In FIG. 1 shows a block diagram of a digital filter; in FIG. 2 is a block diagram of an impulse response register; in FIG. 3 is a block diagram of a polling (reset) register.

The digital filter (see Fig. 1) contains the first 1, second 2, and third 3 blocks of AND elements, a block of 4 OR elements, an adder - a subtractor 5, and a result register 6 forming a filtering channel (CF) 7 _j . The filter also contains a mode trigger 8, registers of the impulse response 9, polling 10 and reset 11, respectively, input 12, blocks of elements NOT 13 and delay 14, inputs of the setting signal of mode 15, impulse response 16, interrogation code 17 and reset code 18, respectively, input 19 clock signals.

 The impulse response register (see Fig. 2) contains two AND 20 and 21 elements, an OR element 22 and a shift register 23, built, for example, on D-triggers.

 The polling (reset) register contains (see FIG. 3) two AND 24, 25 elements, an OR 26 element, and a shift register 27, built, for example, on D-flip-flops.

 The device operates as follows.

 When a single level signal is input to input 15, trigger 8 is set to a single state, the digital filter goes into recording mode. At the same time, feedback chains are broken in registers 9, 10, 11 (K-th trigger of the shift register 23, elements AND 21, OR 22, the first trigger of register 23; K-th trigger of the shift register 27, elements AND 25, OR 26, first the trigger of register 27) and the binary quantized impulse response (ИХ) is recorded in registers 9, 10, 11, supplemented with the length of the “sliding window” by zeros, the interrogation code (QoS), and the reset code (CS) received at the inputs 16, 17 , 18. The shift of information during recording occurs under the influence of a clock signal supplied to input 19.

 The polling code contains one at the position following the last position of THEM, and zeros at all the others.

 The reset code contains one at the position preceding the first weight coefficient of THEM, and zeros at all the others. This ensures that the adder-subtractor KF is set to zero before the arrival of their first weight coefficient.

 After the recording is finished, input 15 is a signal of a single level. Under the influence of the next clock signal, trigger 8 is set to zero. In this case, the feedback circuits in the registers 9, 10, 11 are closed, providing, in the operating mode, synchronous circulation of information in these registers. Synchronism is provided by the arrival of a clock signal at input 19.

 At the information inputs of blocks of elements And 1, 2 of all filtering channels simultaneously received m-bit discrete signal in the forward and reverse codes from the outputs of elements 14 and 13.

 CF 7 is a filter consistent with the signal, the appearance of which is possible at fixed points in time. The detuning in time of arrival of the signal between adjacent CFs is equal to the sampling period T. The minimum value of T should not exceed the processing time of one signal discrete (information delays in the chain of nodes 1 (2), 4, 5, 6, 3. The set K of filtering channels 7 provides signal detection in a "sliding window" of length K, which can be determined by the length THEIR longest of the signals used (the maximum length of the impulse response should not exceed K-2).

The operation of CF 7 begins by setting result register 6 to zero, with a signal of a unit level reset code, coming from the corresponding output of register 11. In the next clock step, the first weight coefficient THEM is fed to the input of channel 7. Each CF provides the accumulation of information in the adder-subtractor 5 and the register 6 in accordance with the values and relative position of the signal and THEM. Depending on the value of the weight coefficient (0 or 1) for an arbitrary KF 7 _j on the clock interval of the discrete input signal is fed to the adder-subtractor 5 or in direct (unit-level signal from the jth inverse output of register 9 at the control input of block 2), or in the reverse (a signal of a unit level from the jth direct output of register 9 at the control input of block 1) code through the corresponding blocks of elements AND, block of elements OR 4. In the latter case, the adder-subtractor 5 also receives a unit in the least significant bit with j- go direct exit reg Istra 9, providing work with additional code.

 After the last weight coefficient of the IC is received at the j-th KF by the signal of the interrogation code of the unit level coming from the j-th output of the register 10 in the next clock interval, the contents of the register of result 6 are received through the block of elements I3 to the output of the filter.

 In the adder-subtractor 5 and the register 6 of the j-th KF, the accumulation of the noise components of the signal through the blocks of elements AND 1, OR 4 continues, but they are not output to the filter. A new cycle of the j-th filtering channel begins with the arrival of a signal of the reset code unit level.

Claims (1)

 A DIGITAL FILTER containing a mode trigger, K filtering channels, each of which contains three blocks of AND elements, a block of OR elements, an adder-subtractor and a result register, impulse response registers and polls, the first, second and third inputs of which are combined and connected respectively to the direct and the inverse outputs of the mode trigger and the input of the clock signal, which is also connected to the first input of the mode trigger, the fourth input of the impulse response register is the input of the impulse response signal, and its j- e direct and inverse outputs are connected respectively to the control inputs of the first and second blocks of elements AND of the j-th filter channel (j = 1, ..., K), the j-th output of the polling register is connected to the control input of the third block of elements, the fourth input which is the input of the polling code signal, the second input of the mode trigger is the input of the mode setting signal, the direct and inverse inputs of the digital filter are connected to the information inputs of the second and first blocks of elements AND of all filtering channels, respectively, in the jth filter channel radios, the outputs of the first and second blocks of AND elements are connected to the inputs of the block of OR elements, the output of which is connected to the first inputs of the adder-subtracter, the jth direct output of the impulse response register is connected to the input of the least significant bit, and the output of the result register connected to the second inputs also with the information inputs of the third block of AND elements, the output of which is the output of the filtering channel, the outputs of the filtering channels are combined and are the output of a digital filter, characterized in that, in order to expand national capabilities due to the processing of signals of various durations, a reset register is introduced, the outputs of which are connected to the installation input in the “0” register of the corresponding filtering channel, information inputs - to the corresponding outputs of the mode trigger, the clock input is the input of the clock signal, and the recording input is the input signal reset code.

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