RU1838894C - Receiver of multifrequency signals - Google Patents

Abstract

The invention relates to devices for receiving multi-frequency signals and can be used in telecommunications. The inventive receiver contains an amplifier with automatic gain control, six band-pass filters, six detectors, a first decoder, first, second and third selectors, signal duration, the first, second, third and fourth elements And, pulse shaper, parallel register, element DISCHARGE, generator, first and second switches, OR element, second decoder, display unit, trigger, one-shot and random access memory unit. 2 s.p. crystals, 3 ill., 1 tab.

Description

Yo

The invention relates to the field of telecommunications and can be used to receive multi-frequency signals.

The purpose of the invention is to increase the noise immunity of received messages.

The proposed device (see fis. Contains an amplifier 1 with automatic gain control, six (2-1,2-2,2-3,2-4,2-5,2-6) narrow-band bandpass filters, six (4-1 , 4- 2.4-3.4-5.4-6) detectors, decoder 6, circuit 7 OR, three (8-1.8-2.8-3) signal selectors by duration, four (9-1 , 9-2.9-3.9-4) circuits And, parallel to 10 register, disambiguation scheme 11, first 12 and second 16 switches, random access memory 13, former 14, generator 15, trigger 17,

counter-18, second decoder 19, display unit 20, one-shot 21.

In FIG. Figure 2 shows the duration selector (8-1.8-2.8-3) of the signal, consisting of an integrating RC circuit 24 and an equivalence circuit 25.

In FIG. 3 shows a shaper 14, consisting of a circuit And 22 and a single vibrator 23,

The multi-frequency signal receiver contains a series-connected amplifier 1 with automatic gain control, six (2-1,2-2,2-3,2-4,2-5,2-6). Narrow-bandpass filters, six (4-1, 4-2.4-3.4-4.4-5.4-6) detectors, the first 6 decoder, the first selector 8-1 signal in duration, the first 9-1 circuit And, parallel 10 register, the first 12 switch, random access memory device00

with

00

00

che

b.

with

13, dynamic display unit 20, serially connected shaper 14, second 16 commutator, counter 18, decoder 19, trigger 17, fourth 9-4 circuit I, connected to the second input of random access memory 13 by output, third connected 8-3 selector signal duration, the third 9-3 AND circuit, output connected to the third input of the first 12 switch, sequentially connected unequal circuit 11, the second 9-2 circuit And, one-shot 21, the output connected to another input of the parallel register 10 , as well as the second 8-2 signal selector in duration, the output connected to the second input of the second 16 decoder, while the 2nd, 3rd, 4th outputs of the decoder 6 are connected respectively to the inputs of the second 8-2 and the third 8- 3 selectors and the input of the shaper 14, the information output of the decoder is connected to the input of the parallel register 10, the input of the ambiguity circuit 11, the second input of the first 12 of the switch, the inputs of the OR circuit 7, respectively, to the output of the decoder 19 and the output of the first 9-1 of the AND circuit, the output of the OR circuit 7 connected to another input of the counter 18.

The operation of this device can be laid down as follows.

When the device is connected to the network, the device is initially reset to its initial state. This operation is performed by applying a Reset signal to the 7th input of the decoder 6. At the outputs of the decoder 6 The allowed combination and the Start are formed of two logical active units. At the Repeat and Digit / Repeat outputs, passive logic zeros are generated. A forbidden code combination 1111 is generated at the information outputs of the decoders (Hereinafter, the superstructure index denotes the number system). The signals from the outputs Start and Enabled combination start the second 8-2 and first 8-1 duration selectors, which are a device that allows the signal to be recognized by duration. In particular, if the duration of the signal that is generated at the four service outputs of the decoder 6 is less than the specified one, then the outputs of the selectors in duration (blocks 8-1, 8-2, 8-3) will have logical zeros. If the incoming output signal of the decoder 6 is greater than the threshold value, then the output of the selectors in duration is a logical unit. This selection operation (see FIG. 2) is achieved

by passing the input signal through the integrating RC circuit and comparing in the circuit of the equivalence of the signals at the input and output of the RC circuit, the RC time constant determines the duration selection operation. For proper operation of the selectors in terms of duration, the ratio

10

0.1 Caraway Caraway Caraway

Here Tmin is the minimum time interval for receiving a multi-frequency transmission. Resetting signal. Reset is always selected as large as minimum.

5 TWH. Therefore, logical units are generated at the output of the first 8-1 and second 8-2 selectors in duration.

In the first 9-1 AND pattern, these signals coincide. At the exit of the first

0 of AND circuit, a nulling signal is generated, which simultaneously enters counter 18, trigger 17, parallel register 10, and forcibly sets the blocks above to their initial state. So counter 18 and trigger 5 ger 1-7 are switched to the zero state, and the parallel register 10 is set to R state 11112. Since trigger 17 is turned to the zero state (QQ, Q 1), the signal from the direct output of the trigger is disabled the operation of the dynamic indication unit 20 is enabled. In addition, the second 16 switch connects the output of the driver 14 to the input of the counter 18. The device is ready to receive signals, the Reset signal can not be supplied to the decoder 6, but in this case, at the initial start-up, the blocks listed above are stored arbitrarily information and. Although when receiving a block of information, the device automatically arrives

0 to working condition.

Consider how signals are received. The received signal is fed through an amplifier 1 with automatic gain control and

5 further in parallel to 6 narrow-band bandpass filters, each of the following -: the bandpass filters above (2-1,2-2,2-3,2-4,2-5,2-6) are tuned to frequencies 700, 900, respectively , 1100, 1300, 1500 and 1700 Hz.

0 It should be noted that a code 2 of 6 can come from the line when operating correctly. This means that only two frequencies from 6 are received at a time. Other combinations, for example one frequency from 6, or more

5 of two frequencies out of 6 are erroneous or prohibited for reception and processing. When a code 2 of 6 arrives at the inputs of narrow-band bandpass filters of this combination, a reception signal can be present at only two outputs. There will be no signal at the other outputs of the bandpass filters. The signals from the output of narrowband bandpass filters are then fed to the inputs of the detectors. This task of the detectors is to detect the received signal. Since only two outputs of the narrow-bandpass filters are present with proper operation, an active logic zero is generated only on the two outputs of the detectors, a passive logic unit is formed on the four remaining outputs of the detectors.

The digital combination from the outputs of the detectors goes further to the input of the decoder 6. The decoder is a read-only memory (ROM), where the output buses of the detectors are the address inputs of the encryption of the ROM for the decoder 6 is given in Table. 1. From the analysis of this table we can conclude that at the input of the decoder 6 there can be only 12 combinations (allowed). 10 combinations - information on the meaning of the transmitted digits. In the decimal number system, such digits are 10 (from 0 to 9). 11th Start combination. Appears at the beginning of the transmission of the information block. 12 combinations - repeat combination. This signal is generated every time in the transmission path when the next transmitted digit in value is the same as the previous one, for example, if we must transmit (and therefore receive a multi-frequency signal receiver) the value of the Zu digit on the i-th and i + 1 clock intervals, then the i-th such interval sends a signal W, and at the i + 1 clock interval, a Turn signal is transmitted. Such an order of transmission and reception of multi-frequency signals carries out a peculiar scrambling. Therefore, adjacent clock signals do not have exactly the same signals. This in turn improves the quality of reception. From an analysis of the code 2 of 6, it can easily be shown that the number of possible combinations with this coding will be 15.

C6

6

2 4

Consequently, the three combinations remain redundant and are prohibited. In addition, all combinations will be prohibited when only one frequency of 6 is received, or more than two frequencies of 6. If the received signal is a permitted combination, then the output of the decoder 6 Allowed combination (hereinafter PK) is a logical unit. If the input combination falls into the forbidden category, then logic zero at the input mentioned above. Other signals are decrypted similarly. Since the Start log is the output, the unit will be only when the 5th signal of the unit 7 is received, the Log unit is formed at the Repeat output when the Repeat signal is received. At the output, a Digit or Repeat is formed. unit when digital information is being received, or when a Retry signal is being received. In the case of receiving a signal, the start at the output of the decoder is 6 digits or Repeat - logic zero, In addition, at the four information outputs of decoder 5 connected to the information inputs of parallel register 10, the received signal 2 of 6 is encoded according to the law 1-2-4- 8. For example, if a combination of the Zu digit is received, then it corresponds to a signal at the information outputs of the decoder 6 0011a. The picture shows the signal reception in more detail. The first received signal is the Start signal. In accordance with the table. 1 on

Active zeros appear at the 5 outputs of detectors 4-1 and 4-6. At the outputs of the decoder 6 RK and Start there will be active logical units. Logic zeros are generated at the Repeat and Digit / Repeat outputs.

0 With the help of the first 8-1 and second 8-2 selectors in duration, a delay interval is formed at the outputs of two logs. units. At the output of the first 9-1 AND circuit, a logical unit appears corresponding to the initial setup signal. If the device is not reset, manually reset, then it is forced to reset to the initial state by the Start signal. The order is exactly the same as for the Reset signal. If the device is already set to its initial state, then the above operations are repeated and the device is again forcedly reset to its original state. Suppose that after receiving the Start signal, we need to receive a block of information consisting of decimal digits 291129. The next signal after receiving

0 The start will be a decimal two signal. In accordance with the table. 1, this signal is received at frequencies fo 700 Hz; fa 1100 Hz. In this case, the following signals will be generated at the decoder output:

5- output of the RK - logical unit.

- output Start - logical zero

- output Repeat - logical zero

- output Digit / Repeat -log.unit. - Information output - code combination 0010.

So, during initial installation, in parallel register 10, the combination 11112 is written in S during the combination. And at the information outputs of the decoder, the combination is 00102, then the second 9-2 circuit I is prepared at the output of the ambiguity circuit 11. With the signal at the output of the first 8-1 selector in duration, the second 9-2 circuit And activates and starts the one-shot 21. Recording in parallel register 10 will be done at the end of the pulse from the output of one-shot 21. As soon as the combination 00102 is written to the parallel register 10, the ambiguity scheme 11 closes. Consequently, the second AND circuit 9-2 closes, and the one-shot 21 will no longer be triggered. This state lasts until the next digit is received and decrypted.

Consider what operations are performed in other blocks. Since at the output of the decoder 6 Repeat is log.null, the third 8-3 selector is turned off by duration. Third 9-3 circuit And closed. The signal from the output of the third 9-3 circuit And the first switch 12 connects the information outputs of the decoder to the information inputs of random access memory 13 (hereinafter RAM 13).

At the output of the decoder 6 Digit / Porator, a log unit is formed. Using the shaper 14, the structure of which is shown in FIG. 3, in the AND 22 circuit, the Digital / Repeat signals coincide with the RK signal. The signal from the output of circuit And 22 starts a single-shot 23, which generates a pulse of a given duration according to formula (1). The second 16 switch connects the output of the driver 14 to the input of the counter 18. The counter 18 is triggered from a given edge of the signal, increasing its state by one. The pulse generated by the duration in the single-shot 23 is used to write information to the RAM 13. At the end of the pulse, the address counter 18 is translated into the RAM 13. The pulse records in the RAM 13 come from the output of the fourth 9-4 circuit I. Since the trigger is installed during initial installation 13 was reset, then at its Q output there is a log unit that allows the fourth 9-4 circuit I to work. When signals of the RK and signals from the output of the former 14 appear, the output of the fourth 9-4 circuit And generates a pulse with a duration equal to single-vibration operation times of the torus 23. The pulse from the output of the fourth 9-4 circuit I. writes at address 00002 — from the output of counter 18, the first digit 0010. As indicated above, at the end of the pulse from the output of former 14, counter 18 goes to state 00012. prepare writing a new number to RAM 13. The decoder 19 remains off while receiving signals, as does the dynamic indication unit 20. The generator 15 is constantly on, but when receiving information, clock pulses from its output do not go anywhere. This is due to the fact that the second switch 16

0 connects the output of the shaper 14 to the input of the counter 18. Similarly to the process described above, the signal 9 is written to the address 00012 in RAM 13. And it is written to the address 0010 1. The situation is different when receiving

5 second decimal unit. In this case, the following signals are generated at the output of the decoder 6

- at the output of the RK - log.unit

- at the output Start - logical zero 0 - at the output Repeat - logical unit

. - at the output Digit / Repeat - log.unit

- at information outputs - combination 11112

5 According to this set of signals, the third 9-3 circuit is triggered AND the first 12 switch connects the output of parallel register 10 to the information inputs of RAM 13. This means that it is necessary to write to RAM 13

0 at the next address information about the previous received character. This information is stored in parallel register 10. Since at the output of decoder 6, the combination is 11112, and at the output of parallel

5 register 10 - combination 00012 then the ambiguity circuit 11 is triggered, starting through the second 9-2 circuit And a single-shot 21. As mentioned above, recording in parallel register 10 is carried out

0 by the trailing edge of the signal from the output of the single-shot 21. Since the first 12 switch, while receiving the Repeat signal, connects the output of the parallel register 10 to the RAM input 13, then the last one at the address 00112

5, the signal 00012 (decimal unit) is recorded again, corresponding to the reception of a fourth digit order. Writing to RAM 13 is similar to writing to the previous three digits. So in

Signal 01102 is written to the memory cell of RAM 13 at address 01002 (the fifth digit is decimal six), and 01102 is written to the cell with address 0101 again, etc. Second decryptor 19 decrypts

5, the state of counter 18. As indicated above, the received information block consisted of 6 decimal digits. After receiving the sixth last digit, the counter 18 enters the state 0110. This state is decrypted by the second decoder 19. At

an active log unit appears at its output, which takes trigger 17 to a single state. If the received block consists of 7 received digits, then the decoder 19 is tuned to the code combination 01112, etc.

| Trigger 17 fires and switches the following devices:

- closes the fourth 9-4 circuit And and thereby prohibits writing to RAM 13,

- switches the output of the generator 15 through the second switch 16 to the input of the counter 10,

- unlocks the operation of the dynamic indication unit 20. L

Oscillator 15 generates clock pulses, which are supplied to counter 18. Counter 18 changes its state from zero to threshold, which is set by decoupler 19. Upon reaching threshold value, counter 18 is received by signal C; the output of the decoder 18 is forcibly zeroed. The state of the counter 18 is used for addressing in the RAM-13 and for operation b) of the dynamic indication 20. From the RAM 10, the first recorded number 2 is read at the zero address. The dynamic indication unit 20 indicates this number at the first Received position. Likewise, the second Accepted position displays the number 9, ..., a | on the sixth, the digit G (for our particular case).

The received block will be displayed until a Reset signal is received, or until a new block of information has arrived.

As the researcher showed, the gain is directly proportional to the frequency deviation

V 4w

where are go-deviations of frequency.

Claims (3)

SUMMARY OF THE INVENTION 1. A multi-frequency signal receiver comprising an amplifier with automatic gain control, six band-pass filters, six detectors, the outputs of which are connected to decoder inputs, a first signal selector in duration, the output of which is connected to the combined first inputs of the first, second, third, and fourth elements And, as well as the OR element, which requires that, in order to increase the noise immunity, consecutively connected parallel register, the first switch, operational block Am minute display unit and sequentially soedinen- nye pulse generator, a second switch, a counter, a second decoder and flip-flop, and the second and third signal selectors in duration NERAVNOZNACH5 element 0 5 0 5 0 5 0 5 0 5 KNOST, a one-shot and generator, the output of which is connected to the second input of the second switch, the third input of which is combined with the second input of the display unit and connected to the output of the trigger, the second input of which is combined with the second input of the random access memory, the first inputs of the OR element and parallel register, and connected to the output of the first element And, the second input of which through the second signal selector is connected in duration to the output of the start of the first decoder, the output of which is Permitted combination of which is connected to the input of the first a signal vector in duration, the output of which is connected to the first input of the pulse former, the second path of which is connected to the output Digit / repeat of the first decoder, the output of which, through the third signal selector, is connected in duration to the second input of the third AND element, the output of which is connected to the second input of the first a switch, the third input of which is combined with the first input of the DISCHARGE element, the second bypass of the parallel register and connected to the additional output of the decoder, the output of the parallel regis through another descent of the element DISEQUALITY is connected to the second input of the second element And, the output of which is connected via a single-vibrator to the third input of the parallel register, the output of the pulse former is connected to the second input of the fourth element And, the output of which is connected to the third input of the RAM block, the fourth the input of which is combined with the third input of the display unit and is connected to the output of the counter, the other input of which is connected to the output of the OR element, the second input of which is combined with the first input of the trigger, inv The forward output of which is connected to the third input of the fourth AND element, the amplifier output with automatic gain control through the corresponding bandpass filters connected to the inputs of six detectors. 2. Receiver pop. 1, characterized in that the signal selector in duration comprises an IDENTITY element, the first input and output of which is the input and output of the signal selector in duration, and the second input of the IDENTITY element is connected to its first input through an integrator. 3. The receiver according to claim 1, with the proviso that the pulse shaper comprises an element And connected in series and a one-shot, the output of which is the output of the pulse shaper, the inputs of which are the inputs of element I. The order of operation of the decoder 6. FO. 700 Hz, F1 900 Hz, F2 1100 Hz, F4 1300 Hz, F7 1500 Hz, F11 1700 Hz. G g | fi 2 1 ON THE fig.Z