RU1828566C - Device for forming of error signal of cycle synchronization - Google Patents

Abstract

Usage: in the electric communication technique, namely, in devices for generating a synchronization error signal. Summary of the invention: a device for generating a synchronization error signal comprises first, second triggers 1, 15, a capacitor 2, a common bus 3, resistors 4, 5.6.7, diodes 8,9,10, elements OR NOT 11, 12,13, element NON 14. The invention provides an increase in the accuracy of generating a loop synchronization error signal. 1 ill.

Description

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The invention relates to electrical communication technology, in particular to devices for generating a synchronization error signal, and may find application for cyclic synchronization of transmitted information,

The purpose of the invention is to improve the accuracy of generating a loop synchronization error signal.

The drawing shows one of the possible variants of the proposed device for generating a cyclic error signal.

The device contains a first trigger 1, a capacitor 2, the first output of which is connected to a common bus 3. As well as the first, second, third and fourth resistors 4-7.

The device also contains the first, second and third diodes 8, 9 and 10, the first, second and third elements OR NOT 11, 12 and 13, the element AND 14 and the second trigger 15. In this case, the first output of the first resistor 4, the anodes of the first and the second diodes 8 and 9 and the cathode of the third diode 10 are connected to the second output of the capacitor 2 and to the information input of the second trigger 15. The direct and inverse outputs of the second trigger 15 are connected respectively to the first input of the first element OR NOT 11 and to the first input of the element And -HE 14, the output of which is connected to the cathode of the first diode 8 through the second p resistor 5. The second input of the AND-NOT 14 element is connected to the second input of the first OR-NOT 11 element, with the first input of the second OR-NOT 12 element and with the inverse output of the first trigger 1. The direct output of the first trigger 1 is connected to the first input of the third element OR 13, with another terminal of the first resistor 4 and with the first terminal of the third resistor 6. The second terminal of the third resistor 6 is connected to the cathode of the second diode 9, and the output of the first element OR NOT 11 is connected through the fourth resistor 7 to the anode of the third diode 10. The outputs of the second and third elements OR NOT 12 and 13 are connected respectively to the input of the installation G and to the input of the installation O of the first trigger 1. The information and clock inputs of the first trigger 1 are respectively the information input 16 of the device and the clock input 17 of the device. The clock input of the second trigger 15 is the input 18 of the device polling signal. The interconnected second inputs of the second and third elements, OR NOT 12 and 13, are the input 19 of the signal for waiting for a pulse of the device clock, and the direct output of this trigger 15 is the output 20 of the device.

The operation of the proposed device for generating a cyclic synchronization error signal is as follows.

From the input 19 of the pulse wait signal

cyclic synchronization of the device to the second inputs of the second and third elements OR-NOT 12 and 13 receives a signal waiting for a pulse of cyclic synchronization, which is a sequence of pulses lasting one period of the signal of the clock pulses coming from the clock input 17 of the device, and a repetition period equal to the period 5 cyclic synchronization pulses. When the signal of waiting for the pulse of cyclic synchronization goes into the state log, 1, at the outputs of the second and third elements OR NOT 12i

0 level log. O, which is supplied to the inputs of the installation O and 1 of the first trigger 1. At the same time, on the positive edge of the clock signal from the clock input 17 of the device to the clock input

5 of the first trigger 1, the information supplied to its information input from the information input 16 of the device is recorded in it. After the transition of the signal for waiting for the pulse of cyclic synchronization to the state of the log. On the output of the second OR-NOT 12 element or at the output of the third OR-NOT 13 element, depending on the information recorded in the first trigger 1, a log level is formed. 1, which arrives at the input of installation 1 or the input of installation О of the first trigger 1 and will confirm the state of the latter until the next occurrence of the log level. 1 at the input 19 of the pulse waiting signal cyclic

0 sync.

In synchronism tracking mode, the second trigger 15 is in a log state. G, and capacitor 2 is charged. If at the expected position of the cyclic synchronization1

5 ma instead of sending a log. D, the package will receive the log. Oh, then the first trigger 1 will be set to log. Oh and the discharge of the capacitor 2 will begin through the second diode 9 and the third resistor 6, as well as through the first

0 resistor 4. If at the expected position of the clock pulse in the information signal, a log message will be received. 1, then the first trigger 1 will enter the log state. 1 and recharging of the capacitor 2 through

5, the first resistor 4. If the clock faults are rare, then the discharge of the capacitor 2 through the third resistor 6 and the second diode 9 will be compensated by charging this capacitor 2 through the first resistor 4. If the clock faults are frequent or if at the expected position of the clock pulse Subject to three or four parcels log. Oh, then the voltage on capacitor 2 will drop below the threshold value and on the positive edge of the polling signal coming from the input 18 of the polling signal of the device, the second trigger 15 will be set to log, 0. and the device will go into sync search mode.

In the clock search mode, the second trigger 15 is in a log state. Oh, and capacitor 2 is discharged. If at the expected position of the clock pulse a log 1 is received, then the first trigger 1 goes to the log state. 1, and at the output, the AND-NOT element 14 sets the log level. 1 and the charging of the capacitor 2 begins through the second resistor 5 and the first diode 8. The constant charging time is seven to eight periods of repetition of pulses of cyclic synchronization. If at the expected position of the sync pulse, seven to eight log messages will be received. 1, then the charge on the capacitor 2 will exceed the threshold value, and the second trigger 15 will go to the log state at the positive edge of the polling signal. 1, and the device goes into synchronism tracking mode. If in the search mode of the clock pulse at the expected position of the clock pulse the message is received. Oh, then the first trigger 1 will go into the log state. Oh, and there will be a quick discharge of the capacitor 2 through the fourth resistor 7 and the third diode 10 through the first element OR NOT 11, the first input of which receives the level log. 1 from the inverse output of the second trigger 15, and to the second input - the log level. 1 with the inverse output of the first trigger 1.

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Claims (1)

SUMMARY OF THE INVENTION A device for generating a cyclic error signal, comprising a first trigger, a capacitor, the first output of which is connected to a common bus, and also first, second, third and fourth resistors, characterized in that, in order to increase the accuracy of generating a signal of a cyclic synchronization error, diodes, OR-NOT elements, AND-NOT element and a second trigger are introduced to it, while the first output of the first resistor, the anodes of the first and second diodes and the cathode of the third diode are connected to the second output of the capacitor and the second trigger input, the direct and inverse outputs of which are connected respectively to the first input of the first OR-NOT element and to the first input of the AND-NOT element, the output of which is connected to the cathode of the first diode through a second resistor, and the second input of the AND-NOT element is connected to the second input of the first OR-NOT element, with the first input of the second OR-NOT element and with the inverse output of the first trigger, the direct output of which is connected to the first input of the third OR-NOT element, with the other terminal of the first resistor and with the first terminal of the third resistor, the second output of which is connected to the cathode of the second diode, the output of the first OR-NOT element is connected through the fourth resistor to the anode of the third diode, and the outputs of the second and third OR-NOT elements are connected respectively to the inputs of the installation in 1 and O, the first trigger, information and clock inputs which are the information and clock inputs of the device, the inputs of the polling signal and the cyclic synchronization signal of which are the clock input of the second trigger and the second inputs of the second and third e ementov NOR.